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626cdca5b6
mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also some ethernet switch initialization code. As we may add more switch support in the future, it's better to move them out of mtk_eth.c to avoid increasing the code complexity. Since not all switches are supported for a particular board, Kconfig options are added to allow user to select which switch should be built into u-boot. If multiple switches are selected, auto-detecting can also be enabled. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
430 lines
12 KiB
C
430 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2025 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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* Author: Mark Lee <mark-mc.lee@mediatek.com>
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*/
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#ifndef _MTK_ETH_H_
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#define _MTK_ETH_H_
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#include <linker_lists.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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struct mtk_eth_priv;
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struct mtk_eth_switch_priv;
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/* struct mtk_soc_data - This is the structure holding all differences
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* among various plaforms
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* @caps Flags shown the extra capability for the SoC
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* @ana_rgc3: The offset for register ANA_RGC3 related to
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* sgmiisys syscon
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* @gdma_count: Number of GDMAs
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* @pdma_base: Register base of PDMA block
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* @txd_size: Tx DMA descriptor size.
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* @rxd_size: Rx DMA descriptor size.
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*/
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struct mtk_soc_data {
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u32 caps;
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u32 ana_rgc3;
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u32 gdma_count;
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u32 pdma_base;
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u32 txd_size;
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u32 rxd_size;
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};
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struct mtk_eth_switch {
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const char *name;
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const char *desc;
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size_t priv_size;
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u32 reset_wait_time;
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int (*detect)(struct mtk_eth_priv *priv);
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int (*setup)(struct mtk_eth_switch_priv *priv);
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int (*cleanup)(struct mtk_eth_switch_priv *priv);
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void (*mac_control)(struct mtk_eth_switch_priv *priv, bool enable);
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};
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#define MTK_ETH_SWITCH(__name) \
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ll_entry_declare(struct mtk_eth_switch, __name, mtk_eth_switch)
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struct mtk_eth_switch_priv {
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struct mtk_eth_priv *eth;
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const struct mtk_eth_switch *sw;
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const struct mtk_soc_data *soc;
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void *ethsys_base;
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int phy_interface;
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};
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enum mkt_eth_capabilities {
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MTK_TRGMII_BIT,
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MTK_TRGMII_MT7621_CLK_BIT,
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MTK_U3_COPHY_V2_BIT,
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MTK_INFRA_BIT,
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MTK_NETSYS_V2_BIT,
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MTK_NETSYS_V3_BIT,
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/* PATH BITS */
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MTK_ETH_PATH_GMAC1_TRGMII_BIT,
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MTK_ETH_PATH_GMAC2_SGMII_BIT,
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MTK_ETH_PATH_MT7622_SGMII_BIT,
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MTK_ETH_PATH_MT7629_GMAC2_BIT,
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};
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#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
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#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
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#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
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#define MTK_INFRA BIT(MTK_INFRA_BIT)
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#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
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#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT)
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/* Supported path present on SoCs */
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#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
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#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
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#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
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#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT)
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#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
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#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
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#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
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#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
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#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII)
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#define MT7623_CAPS (MTK_GMAC1_TRGMII)
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#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA)
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#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
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#define MT7986_CAPS (MTK_NETSYS_V2)
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#define MT7987_CAPS (MTK_NETSYS_V3 | MTK_GMAC2_U3_QPHY | MTK_INFRA)
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#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA)
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/* Frame Engine Register Bases */
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#define PDMA_V1_BASE 0x0800
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#define PDMA_V2_BASE 0x6000
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#define PDMA_V3_BASE 0x6800
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#define GDMA1_BASE 0x0500
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#define GDMA2_BASE 0x1500
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#define GDMA3_BASE 0x0540
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#define GMAC_BASE 0x10000
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#define GSW_BASE 0x20000
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/* Ethernet subsystem registers */
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#define ETHSYS_SYSCFG1_REG 0x14
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#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
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#define SYSCFG1_GE_MODE_M 0x3
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#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8)
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#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac))
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#define ETHSYS_CLKCFG0_REG 0x2c
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#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
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/* Top misc registers */
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#define TOPMISC_NETSYS_PCS_MUX 0x84
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#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
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#define MUX_G2_USXGMII_SEL BIT(1)
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#define MUX_HSGMII1_G1_SEL BIT(0)
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#define USB_PHY_SWITCH_REG 0x218
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#define QPHY_SEL_MASK 0x3
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#define SGMII_QPHY_SEL 0x2
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#define MT7629_INFRA_MISC2_REG 0x70c
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#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0)
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/* SYSCFG1_GE_MODE: GE Modes */
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#define GE_MODE_RGMII 0
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#define GE_MODE_MII 1
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#define GE_MODE_MII_PHY 2
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#define GE_MODE_RMII 3
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/* SGMII subsystem config registers */
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#define SGMSYS_PCS_CONTROL_1 0x0
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#define SGMII_LINK_STATUS BIT(18)
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#define SGMII_AN_ENABLE BIT(12)
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#define SGMII_AN_RESTART BIT(9)
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#define SGMSYS_SGMII_MODE 0x20
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#define SGMII_AN_MODE 0x31120103
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#define SGMII_FORCE_MODE 0x31120019
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#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
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#define SGMII_PHYA_PWD BIT(4)
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#define SGMSYS_QPHY_WRAP_CTRL 0xec
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#define SGMII_PN_SWAP_TX_RX 0x03
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#define SGMSYS_GEN2_SPEED 0x2028
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#define SGMSYS_GEN2_SPEED_V2 0x128
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#define SGMSYS_SPEED_MASK GENMASK(3, 2)
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#define SGMSYS_SPEED_2500 1
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/* USXGMII subsystem config registers */
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/* Register to control USXGMII XFI PLL digital */
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#define XFI_PLL_DIG_GLB8 0x08
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#define RG_XFI_PLL_EN BIT(31)
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/* Register to control USXGMII XFI PLL analog */
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#define XFI_PLL_ANA_GLB8 0x108
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#define RG_XFI_PLL_ANA_SWWA 0x02283248
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/* Frame Engine Registers */
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#define PSE_NO_DROP_CFG_REG 0x108
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#define PSE_NO_DROP_GDM1 BIT(1)
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#define FE_GLO_MISC_REG 0x124
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#define PDMA_VER_V2 BIT(4)
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/* PDMA */
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#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
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#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
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#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
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#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
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#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
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#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
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#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
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#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
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#define PDMA_GLO_CFG_REG 0x204
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#define TX_WB_DDONE BIT(6)
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#define RX_DMA_BUSY BIT(3)
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#define RX_DMA_EN BIT(2)
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#define TX_DMA_BUSY BIT(1)
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#define TX_DMA_EN BIT(0)
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#define PDMA_RST_IDX_REG 0x208
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#define RST_DRX_IDX0 BIT(16)
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#define RST_DTX_IDX0 BIT(0)
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/* GDMA */
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#define GDMA_IG_CTRL_REG 0x000
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#define GDM_ICS_EN BIT(22)
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#define GDM_TCS_EN BIT(21)
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#define GDM_UCS_EN BIT(20)
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#define STRP_CRC BIT(16)
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#define MYMAC_DP_S 12
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#define MYMAC_DP_M 0xf000
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#define BC_DP_S 8
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#define BC_DP_M 0xf00
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#define MC_DP_S 4
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#define MC_DP_M 0xf0
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#define UN_DP_S 0
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#define UN_DP_M 0x0f
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#define GDMA_EG_CTRL_REG 0x004
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#define GDMA_CPU_BRIDGE_EN BIT(31)
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#define GDMA_MAC_LSB_REG 0x008
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#define GDMA_MAC_MSB_REG 0x00c
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/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
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#define DP_PDMA 0
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#define DP_GDMA1 1
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#define DP_GDMA2 2
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#define DP_PPE 4
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#define DP_QDMA 5
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#define DP_DISCARD 7
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/* GMAC Registers */
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#define GMAC_PPSC_REG 0x0000
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#define PHY_MDC_CFG GENMASK(29, 24)
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#define MDC_TURBO BIT(20)
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#define MDC_MAX_FREQ 25000000
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#define MDC_MAX_DIVIDER 63
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#define GMAC_PIAC_REG 0x0004
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#define PHY_ACS_ST BIT(31)
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#define MDIO_REG_ADDR_S 25
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#define MDIO_REG_ADDR_M 0x3e000000
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#define MDIO_PHY_ADDR_S 20
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#define MDIO_PHY_ADDR_M 0x1f00000
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#define MDIO_CMD_S 18
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#define MDIO_CMD_M 0xc0000
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#define MDIO_ST_S 16
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#define MDIO_ST_M 0x30000
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#define MDIO_RW_DATA_S 0
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#define MDIO_RW_DATA_M 0xffff
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#define GMAC_XGMAC_STS_REG 0x000c
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#define P1_XGMAC_FORCE_LINK BIT(15)
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#define GMAC_MAC_MISC_REG 0x0010
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#define MISC_MDC_TURBO BIT(4)
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#define GMAC_GSW_CFG_REG 0x0080
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#define GSWTX_IPG_M 0xF0000
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#define GSWTX_IPG_S 16
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#define GSWRX_IPG_M 0xF
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#define GSWRX_IPG_S 0
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/* MDIO_CMD: MDIO commands */
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#define MDIO_CMD_ADDR 0
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#define MDIO_CMD_WRITE 1
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#define MDIO_CMD_READ 2
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#define MDIO_CMD_READ_C45 3
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/* MDIO_ST: MDIO start field */
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#define MDIO_ST_C45 0
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#define MDIO_ST_C22 1
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#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
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#define MAC_RX_PKT_LEN_S 24
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#define MAC_RX_PKT_LEN_M 0x3000000
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#define IPG_CFG_S 18
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#define IPG_CFG_M 0xc0000
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#define MAC_MODE BIT(16)
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#define FORCE_MODE BIT(15)
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#define MAC_TX_EN BIT(14)
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#define MAC_RX_EN BIT(13)
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#define DEL_RXFIFO_CLR BIT(12)
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#define BKOFF_EN BIT(9)
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#define BACKPR_EN BIT(8)
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#define FORCE_RX_FC BIT(5)
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#define FORCE_TX_FC BIT(4)
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#define FORCE_SPD_S 2
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#define FORCE_SPD_M 0x0c
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#define FORCE_DPX BIT(1)
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#define FORCE_LINK BIT(0)
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/* Values of IPG_CFG */
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#define IPG_96BIT 0
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#define IPG_96BIT_WITH_SHORT_IPG 1
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#define IPG_64BIT 2
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/* MAC_RX_PKT_LEN: Max RX packet length */
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#define MAC_RX_PKT_LEN_1518 0
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#define MAC_RX_PKT_LEN_1536 1
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#define MAC_RX_PKT_LEN_1552 2
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#define MAC_RX_PKT_LEN_JUMBO 3
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/* FORCE_SPD: Forced link speed */
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#define SPEED_10M 0
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#define SPEED_100M 1
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#define SPEED_1000M 2
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#define GMAC_TRGMII_RCK_CTRL 0x300
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#define RX_RST BIT(31)
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#define RXC_DQSISEL BIT(30)
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#define NUM_TRGMII_CTRL 5
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#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
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#define TD_DM_DRVN_S 4
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#define TD_DM_DRVN_M 0xf0
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#define TD_DM_DRVP_S 0
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#define TD_DM_DRVP_M 0x0f
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/* XGMAC Status Registers */
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#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C)
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#define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15))
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/* XGMAC Registers */
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#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000))
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#define XGMAC_TRX_DISABLE 0xf
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#define XGMAC_FORCE_TX_FC BIT(5)
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#define XGMAC_FORCE_RX_FC BIT(4)
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/* MDIO Indirect Access Registers */
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#define MII_MMD_ACC_CTL_REG 0x0d
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#define MMD_CMD_S 14
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#define MMD_CMD_M 0xc000
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#define MMD_DEVAD_S 0
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#define MMD_DEVAD_M 0x1f
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/* MMD_CMD: MMD commands */
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#define MMD_ADDR 0
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#define MMD_DATA 1
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#define MMD_DATA_RW_POST_INC 2
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#define MMD_DATA_W_POST_INC 3
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#define MII_MMD_ADDR_DATA_REG 0x0e
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/* PDMA descriptors */
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struct mtk_rx_dma {
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unsigned int rxd1;
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unsigned int rxd2;
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unsigned int rxd3;
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unsigned int rxd4;
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} __packed __aligned(4);
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struct mtk_rx_dma_v2 {
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unsigned int rxd1;
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unsigned int rxd2;
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unsigned int rxd3;
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unsigned int rxd4;
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unsigned int rxd5;
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unsigned int rxd6;
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unsigned int rxd7;
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unsigned int rxd8;
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} __packed __aligned(4);
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struct mtk_tx_dma {
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unsigned int txd1;
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unsigned int txd2;
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unsigned int txd3;
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unsigned int txd4;
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} __packed __aligned(4);
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struct mtk_tx_dma_v2 {
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unsigned int txd1;
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unsigned int txd2;
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unsigned int txd3;
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unsigned int txd4;
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unsigned int txd5;
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unsigned int txd6;
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unsigned int txd7;
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unsigned int txd8;
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} __packed __aligned(4);
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/* PDMA TXD fields */
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#define PDMA_TXD2_DDONE BIT(31)
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#define PDMA_TXD2_LS0 BIT(30)
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#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16)
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#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v))
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#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8)
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#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v))
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#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25)
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#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v))
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#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24)
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#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v))
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#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16)
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#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v))
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/* PDMA RXD fields */
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#define PDMA_RXD2_DDONE BIT(31)
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#define PDMA_RXD2_LS0 BIT(30)
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#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16)
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#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v))
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#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v))
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#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8)
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#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v))
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#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v))
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void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set);
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void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set);
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void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set);
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int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg);
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int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data);
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int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
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int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
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u16 val);
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int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
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int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
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u16 val);
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#endif /* _MTK_ETH_H_ */
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