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626cdca5b6
mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also some ethernet switch initialization code. As we may add more switch support in the future, it's better to move them out of mtk_eth.c to avoid increasing the code complexity. Since not all switches are supported for a particular board, Kconfig options are added to allow user to select which switch should be built into u-boot. If multiple switches are selected, auto-detecting can also be enabled. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
287 lines
8.2 KiB
C
287 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2025 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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* Author: Mark Lee <mark-mc.lee@mediatek.com>
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*/
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#ifndef _MTK_ETH_MT753X_H_
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#define _MTK_ETH_MT753X_H_
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#include <phy.h>
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#include <miiphy.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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struct mtk_eth_priv;
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#define MT753X_NUM_PHYS 5
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#define MT753X_NUM_PORTS 7
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#define MT753X_DFL_SMI_ADDR 31
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#define MT753X_SMI_ADDR_MASK 0x1f
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#define MT753X_PHY_ADDR(base, addr) \
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(((base) + (addr)) & 0x1f)
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/* MT7530 Registers */
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#define PCR_REG(p) (0x2004 + (p) * 0x100)
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#define PORT_MATRIX_S 16
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#define PORT_MATRIX_M 0xff0000
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#define PVC_REG(p) (0x2010 + (p) * 0x100)
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#define STAG_VPID_S 16
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#define STAG_VPID_M 0xffff0000
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#define VLAN_ATTR_S 6
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#define VLAN_ATTR_M 0xc0
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/* VLAN_ATTR: VLAN attributes */
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#define VLAN_ATTR_USER 0
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#define VLAN_ATTR_STACK 1
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#define VLAN_ATTR_TRANSLATION 2
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#define VLAN_ATTR_TRANSPARENT 3
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#define PMCR_REG(p) (0x3000 + (p) * 0x100)
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/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
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* MT7531 specific fields are defined below
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*/
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#define FORCE_MODE_EEE1G BIT(25)
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#define FORCE_MODE_EEE100 BIT(26)
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#define FORCE_MODE_TX_FC BIT(27)
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#define FORCE_MODE_RX_FC BIT(28)
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#define FORCE_MODE_DPX BIT(29)
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#define FORCE_MODE_SPD BIT(30)
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#define FORCE_MODE_LNK BIT(31)
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#define MT7531_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
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FORCE_MODE_DPX | FORCE_MODE_SPD | \
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FORCE_MODE_LNK
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#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
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FORCE_MODE_DPX | FORCE_MODE_SPD | \
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FORCE_MODE_LNK
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/* MT7531 SGMII Registers */
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#define MT7531_SGMII_REG_BASE 0x5000
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#define MT7531_SGMII_REG_PORT_BASE 0x1000
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#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
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(p) * MT7531_SGMII_REG_PORT_BASE + (r))
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#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00)
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#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20)
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#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8)
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#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128)
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#define MT7531_PHYA_ANA_SYSPLL(p) MT7531_SGMII_REG(((p) - 5), 0x158)
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/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */
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/* MT753x System Control Register */
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#define SYS_CTRL_REG 0x7000
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#define SW_PHY_RST BIT(2)
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#define SW_SYS_RST BIT(1)
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#define SW_REG_RST BIT(0)
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/* MT7531 */
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#define MT7531_PHY_IAC 0x701c
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/* XXX: all fields are defined under GMAC_PIAC_REG */
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#define MT7531_CLKGEN_CTRL 0x7500
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#define CLK_SKEW_OUT_S 8
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#define CLK_SKEW_OUT_M 0x300
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#define CLK_SKEW_IN_S 6
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#define CLK_SKEW_IN_M 0xc0
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#define RXCLK_NO_DELAY BIT(5)
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#define TXCLK_NO_REVERSE BIT(4)
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#define GP_MODE_S 1
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#define GP_MODE_M 0x06
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#define GP_CLK_EN BIT(0)
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/* Values of GP_MODE */
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#define GP_MODE_RGMII 0
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#define GP_MODE_MII 1
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#define GP_MODE_REV_MII 2
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/* Values of CLK_SKEW_IN */
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#define CLK_SKEW_IN_NO_CHANGE 0
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#define CLK_SKEW_IN_DELAY_100PPS 1
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#define CLK_SKEW_IN_DELAY_200PPS 2
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#define CLK_SKEW_IN_REVERSE 3
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/* Values of CLK_SKEW_OUT */
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#define CLK_SKEW_OUT_NO_CHANGE 0
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#define CLK_SKEW_OUT_DELAY_100PPS 1
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#define CLK_SKEW_OUT_DELAY_200PPS 2
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#define CLK_SKEW_OUT_REVERSE 3
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#define HWTRAP_REG 0x7800
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/* MT7530 Modified Hardware Trap Status Registers */
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#define MHWTRAP_REG 0x7804
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#define CHG_TRAP BIT(16)
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#define LOOPDET_DIS BIT(14)
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#define P5_INTF_SEL_S 13
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#define P5_INTF_SEL_M 0x2000
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#define SMI_ADDR_S 11
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#define SMI_ADDR_M 0x1800
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#define XTAL_FSEL_S 9
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#define XTAL_FSEL_M 0x600
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#define P6_INTF_DIS BIT(8)
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#define P5_INTF_MODE_S 7
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#define P5_INTF_MODE_M 0x80
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#define P5_INTF_DIS BIT(6)
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#define C_MDIO_BPS BIT(5)
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#define CHIP_MODE_S 0
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#define CHIP_MODE_M 0x0f
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/* P5_INTF_SEL: Interface type of Port5 */
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#define P5_INTF_SEL_GPHY 0
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#define P5_INTF_SEL_GMAC5 1
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/* P5_INTF_MODE: Interface mode of Port5 */
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#define P5_INTF_MODE_GMII_MII 0
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#define P5_INTF_MODE_RGMII 1
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#define MT7530_P6ECR 0x7830
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#define P6_INTF_MODE_M 0x3
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#define P6_INTF_MODE_S 0
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/* P6_INTF_MODE: Interface mode of Port6 */
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#define P6_INTF_MODE_RGMII 0
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#define P6_INTF_MODE_TRGMII 1
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#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
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#define RD_TAP_S 0
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#define RD_TAP_M 0x7f
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#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
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/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
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/* TOP Signals Status Register */
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#define MT7531_TOP_SIG_SR 0x780c
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#define PAD_MCM_SMI_EN BIT(0)
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#define PAD_DUAL_SGMII_EN BIT(1)
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/* MT7531 PLLGP Registers */
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#define MT7531_PLLGP_EN 0x7820
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#define EN_COREPLL BIT(2)
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#define SW_CLKSW BIT(1)
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#define SW_PLLGP BIT(0)
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#define MT7531_PLLGP_CR0 0x78a8
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#define RG_COREPLL_EN BIT(22)
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#define RG_COREPLL_POSDIV_S 23
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#define RG_COREPLL_POSDIV_M 0x3800000
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#define RG_COREPLL_SDM_PCW_S 1
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#define RG_COREPLL_SDM_PCW_M 0x3ffffe
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#define RG_COREPLL_SDM_PCW_CHG BIT(0)
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/* MT7531 RGMII and SGMII PLL clock */
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#define MT7531_ANA_PLLGP_CR2 0x78b0
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#define MT7531_ANA_PLLGP_CR5 0x78bc
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/* MT7531 GPIO GROUP IOLB SMT0 Control */
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#define MT7531_SMT0_IOLB 0x7f04
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#define SMT_IOLB_5_SMI_MDC_EN BIT(5)
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/* MT7530 GPHY MDIO MMD Registers */
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#define CORE_PLL_GROUP2 0x401
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#define RG_SYSPLL_EN_NORMAL BIT(15)
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#define RG_SYSPLL_VODEN BIT(14)
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#define RG_SYSPLL_POSDIV_S 5
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#define RG_SYSPLL_POSDIV_M 0x60
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#define CORE_PLL_GROUP4 0x403
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#define MT7531_BYPASS_MODE BIT(4)
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#define MT7531_POWER_ON_OFF BIT(5)
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#define RG_SYSPLL_DDSFBK_EN BIT(12)
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#define RG_SYSPLL_BIAS_EN BIT(11)
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#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
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#define CORE_PLL_GROUP5 0x404
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#define RG_LCDDS_PCW_NCPO1_S 0
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#define RG_LCDDS_PCW_NCPO1_M 0xffff
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#define CORE_PLL_GROUP6 0x405
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#define RG_LCDDS_PCW_NCPO0_S 0
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#define RG_LCDDS_PCW_NCPO0_M 0xffff
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#define CORE_PLL_GROUP7 0x406
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#define RG_LCDDS_PWDB BIT(15)
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#define RG_LCDDS_ISO_EN BIT(13)
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#define RG_LCCDS_C_S 4
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#define RG_LCCDS_C_M 0x70
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#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
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#define CORE_PLL_GROUP10 0x409
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#define RG_LCDDS_SSC_DELTA_S 0
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#define RG_LCDDS_SSC_DELTA_M 0xfff
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#define CORE_PLL_GROUP11 0x40a
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#define RG_LCDDS_SSC_DELTA1_S 0
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#define RG_LCDDS_SSC_DELTA1_M 0xfff
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#define CORE_GSWPLL_GRP1 0x40d
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#define RG_GSWPLL_POSDIV_200M_S 12
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#define RG_GSWPLL_POSDIV_200M_M 0x3000
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#define RG_GSWPLL_EN_PRE BIT(11)
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#define RG_GSWPLL_FBKDIV_200M_S 0
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#define RG_GSWPLL_FBKDIV_200M_M 0xff
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#define CORE_GSWPLL_GRP2 0x40e
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#define RG_GSWPLL_POSDIV_500M_S 8
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#define RG_GSWPLL_POSDIV_500M_M 0x300
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#define RG_GSWPLL_FBKDIV_500M_S 0
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#define RG_GSWPLL_FBKDIV_500M_M 0xff
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#define CORE_TRGMII_GSW_CLK_CG 0x410
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#define REG_GSWCK_EN BIT(0)
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#define REG_TRGMIICK_EN BIT(1)
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/* Extend PHY Control Register 3 */
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#define PHY_EXT_REG_14 0x14
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/* Fields of PHY_EXT_REG_14 */
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#define PHY_EN_DOWN_SHFIT BIT(4)
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/* Extend PHY Control Register 4 */
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#define PHY_EXT_REG_17 0x17
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/* Fields of PHY_EXT_REG_17 */
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#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
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/* PHY RXADC Control Register 7 */
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#define PHY_DEV1E_REG_0C6 0x0c6
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/* Fields of PHY_DEV1E_REG_0C6 */
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#define PHY_POWER_SAVING_S 8
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#define PHY_POWER_SAVING_M 0x300
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#define PHY_POWER_SAVING_TX 0x0
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struct mt753x_switch_priv {
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struct mtk_eth_switch_priv epriv;
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struct mii_dev *mdio_bus;
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u32 smi_addr;
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u32 phy_base;
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u32 pmcr;
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int (*reg_read)(struct mt753x_switch_priv *priv, u32 reg, u32 *data);
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int (*reg_write)(struct mt753x_switch_priv *priv, u32 reg, u32 data);
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};
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int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg,
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u32 *data);
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int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data);
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int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data);
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int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data);
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int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data);
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void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set);
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int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg);
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int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val);
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int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad,
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u16 reg);
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int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad,
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u16 reg, u16 val);
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int mt7531_mdio_register(struct mt753x_switch_priv *priv);
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void mt753x_port_isolation(struct mt753x_switch_priv *priv);
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#endif /* _MTK_ETH_MT753X_H_ */
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