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u-boot/drivers/clk/qcom/clock-sm8250.c
Caleb Connolly 7c5460afec
clk/qcom: bubble up qcom_gate_clk_en() errors 
If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.

Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-03-17 15:12:15 +00:00

396 lines
14 KiB
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Clock drivers for Qualcomm sm8250
*
* (C) Copyright 2024 Linaro Ltd.
*/
#include <clk-uclass.h>
#include <dm.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/bug.h>
#include <linux/bitops.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include "clock-qcom.h"
#define GCC_SE12_UART_RCG_REG 0x184D0
#define GCC_SDCC2_APPS_CLK_SRC_REG 0x1400c
#define APCS_GPLL0_ENA_VOTE 0x79000
#define APCS_GPLL9_STATUS 0x1c000
#define APCS_GPLLX_ENA_REG 0x52018
#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf064
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = {
F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
{}
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0),
{}
};
static struct pll_vote_clk gpll9_vote_clk = {
.status = APCS_GPLL9_STATUS,
.status_bit = BIT(31),
.ena_vote = APCS_GPLLX_ENA_REG,
.vote_bit = BIT(9),
};
static ulong sm8250_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
const struct freq_tbl *freq;
if (clk->id < priv->data->num_clks)
debug("%s: %s, requested rate=%ld\n", __func__,
priv->data->clks[clk->id].name, rate);
switch (clk->id) {
case GCC_QUPV3_WRAP1_S4_CLK: /*UART2*/
freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s4_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, GCC_SE12_UART_RCG_REG,
freq->pre_div, freq->m, freq->n, freq->src,
16);
return freq->freq;
case GCC_SDCC2_APPS_CLK:
/* Enable GPLL9 so that we can point SDCC2_APPS_CLK_SRC at it */
clk_enable_gpll0(priv->base, &gpll9_vote_clk);
freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
printf("%s: got freq %u\n", __func__, freq->freq);
WARN(freq->src != CFG_CLK_SRC_GPLL9,
"SDCC2_APPS_CLK_SRC not set to GPLL9, requested rate %lu\n",
rate);
clk_rcg_set_rate_mnd(priv->base, GCC_SDCC2_APPS_CLK_SRC_REG,
freq->pre_div, freq->m, freq->n,
CFG_CLK_SRC_GPLL9, 8);
return rate;
default:
return 0;
}
}
static const struct gate_clk sm8250_clks[] = {
GATE_CLK(GCC_AGGRE_UFS_CARD_AXI_CLK, 0x750cc, 0x00000001),
GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, 0x00000001),
GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x0f080, 0x00000001),
GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x10080, 0x00000001),
GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x0f07c, 0x00000001),
GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x1007c, 0x00000001),
GATE_CLK(GCC_QMIP_CAMERA_NRT_AHB_CLK, 0x0b018, 0x00000001),
GATE_CLK(GCC_QMIP_CAMERA_RT_AHB_CLK, 0x0b01c, 0x00000001),
GATE_CLK(GCC_QMIP_DISP_AHB_CLK, 0x0b020, 0x00000001),
GATE_CLK(GCC_QMIP_VIDEO_CVP_AHB_CLK, 0x0b010, 0x00000001),
GATE_CLK(GCC_QMIP_VIDEO_VCODEC_AHB_CLK, 0x0b014, 0x00000001),
GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x52008, 0x00000200),
GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x52008, 0x00000100),
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, 0x00000400),
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, 0x00000800),
GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x52008, 0x00001000),
GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, 0x00002000),
GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x52008, 0x00004000),
GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, 0x00008000),
GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x52008, 0x00010000),
GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, 0x00020000),
GATE_CLK(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x52008, 0x00040000),
GATE_CLK(GCC_QUPV3_WRAP1_CORE_CLK, 0x52008, 0x00080000),
GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x52008, 0x00400000),
GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, 0x00800000),
GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x52008, 0x01000000),
GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x52008, 0x02000000),
GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x52008, 0x04000000),
GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x52008, 0x08000000),
GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, 0x00000008),
GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, 0x00000001),
GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, 0x00000010),
GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, 0x00000020),
GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, 0x00000040),
GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, 0x00000080),
GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, 0x00000100),
GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, 0x00000200),
GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x52008, 0x00000040),
GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x52008, 0x00000080),
GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x52008, 0x00100000),
GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x52008, 0x00200000),
GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, 0x00000004),
GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, 0x00000002),
GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001),
GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001),
GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001),
GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001),
GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75018, 0x00000001),
GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x75010, 0x00000001),
GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75064, 0x00000001),
GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7509c, 0x00000001),
GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75020, 0x00000001),
GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750b8, 0x00000001),
GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x7501c, 0x00000001),
GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x7505c, 0x00000001),
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, 0x00000001),
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, 0x00000001),
GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, 0x00000001),
GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, 0x00000001),
GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, 0x00000001),
GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, 0x00000001),
GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, 0x00000001),
GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, 0x00000001),
GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f010, 0x00000001),
GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f01c, 0x00000001),
GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f018, 0x00000001),
GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x10010, 0x00000001),
GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x1001c, 0x00000001),
GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10018, 0x00000001),
GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f054, 0x00000001),
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f058, 0x00000001),
GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f05c, 0x00000001),
GATE_CLK(GCC_USB3_SEC_CLKREF_EN, 0x8c010, 0x00000001),
GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x10054, 0x00000001),
GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10058, 0x00000001),
GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x1005c, 0x00000001),
};
static int sm8250_enable(struct clk *clk)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
if (priv->data->num_clks < clk->id) {
debug("%s: unknown clk id %lu\n", __func__, clk->id);
return 0;
}
debug("%s: clk %s\n", __func__, sm8250_clks[clk->id].name);
switch (clk->id) {
case GCC_USB30_PRIM_MASTER_CLK:
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
break;
case GCC_USB30_SEC_MASTER_CLK:
qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
break;
}
return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sm8250_gcc_resets[] = {
[GCC_GPU_BCR] = { 0x71000 },
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_NPU_BWMON_BCR] = { 0x73000 },
[GCC_NPU_BCR] = { 0x4d000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
[GCC_PCIE_2_BCR] = { 0x6000 },
[GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
[GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_PRNG_BCR] = { 0x34000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
[GCC_UFS_CARD_BCR] = { 0x75000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
static const struct qcom_power_map sm8250_gdscs[] = {
[PCIE_0_GDSC] = { 0x6b004 }, [PCIE_1_GDSC] = { 0x8d004 },
[PCIE_2_GDSC] = { 0x6004 }, [UFS_CARD_GDSC] = { 0x75004 },
[UFS_PHY_GDSC] = { 0x77004 }, [USB30_PRIM_GDSC] = { 0xf004 },
[USB30_SEC_GDSC] = { 0x10004 },
};
static const phys_addr_t sm8250_gpll_addrs[] = {
0x00100000, // GCC_GPLL0_MODE
0x00101000, // GCC_GPLL1_MODE
0x00102000, // GCC_GPLL2_MODE
0x00103000, // GCC_GPLL3_MODE
0x00176000, // GCC_GPLL4_MODE
0x00174000, // GCC_GPLL5_MODE
0x00113000, // GCC_GPLL6_MODE
0x0011a000, // GCC_GPLL7_MODE
0x0011b000, // GCC_GPLL8_MODE
0x0011c000, // GCC_GPLL9_MODE
0x0011d000, // GCC_GPLL10_MODE
0x0014a000, // GCC_GPLL11_MODE
};
static const phys_addr_t sm8250_rcg_addrs[] = {
0x0010f020, // GCC_USB30_PRIM_MASTER_CMD_RCGR
0x0010f038, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR
0x0010f064, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR
0x00110020, // GCC_USB30_SEC_MASTER_CMD_RCGR
0x00110038, // GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR
0x00110064, // GCC_USB3_SEC_PHY_AUX_CMD_RCGR
0x0011400c, // GCC_SDCC2_APPS_CMD_RCGR
0x0011600c, // GCC_SDCC4_APPS_CMD_RCGR
0x0012300c, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR
0x00117010, // GCC_QUPV3_WRAP0_S0_CMD_RCGR
0x00117140, // GCC_QUPV3_WRAP0_S1_CMD_RCGR
0x00117270, // GCC_QUPV3_WRAP0_S2_CMD_RCGR
0x001173a0, // GCC_QUPV3_WRAP0_S3_CMD_RCGR
0x001174d0, // GCC_QUPV3_WRAP0_S4_CMD_RCGR
0x00117600, // GCC_QUPV3_WRAP0_S5_CMD_RCGR
0x00117730, // GCC_QUPV3_WRAP0_S6_CMD_RCGR
0x00117860, // GCC_QUPV3_WRAP0_S7_CMD_RCGR
0x00123144, // GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR
0x00118010, // GCC_QUPV3_WRAP1_S0_CMD_RCGR
0x00118140, // GCC_QUPV3_WRAP1_S1_CMD_RCGR
0x00118270, // GCC_QUPV3_WRAP1_S2_CMD_RCGR
0x001183a0, // GCC_QUPV3_WRAP1_S3_CMD_RCGR
0x001184d0, // GCC_QUPV3_WRAP1_S4_CMD_RCGR
0x00118600, // GCC_QUPV3_WRAP1_S5_CMD_RCGR
0x0016b038, // GCC_PCIE_0_AUX_CMD_RCGR
0x0018d038, // GCC_PCIE_1_AUX_CMD_RCGR
0x0016f014, // GCC_PCIE_PHY_REFGEN_CMD_RCGR
0x00175024, // GCC_UFS_CARD_AXI_CMD_RCGR
0x0017506c, // GCC_UFS_CARD_ICE_CORE_CMD_RCGR
0x00175084, // GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR
0x001750a0, // GCC_UFS_CARD_PHY_AUX_CMD_RCGR
0x00177024, // GCC_UFS_PHY_AXI_CMD_RCGR
0x0017706c, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR
0x00177084, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR
0x001770a0, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR
0x0012327c, // GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR
0x0011e010, // GCC_QUPV3_WRAP2_S0_CMD_RCGR
0x0011e140, // GCC_QUPV3_WRAP2_S1_CMD_RCGR
0x0011e270, // GCC_QUPV3_WRAP2_S2_CMD_RCGR
0x0011e3a0, // GCC_QUPV3_WRAP2_S3_CMD_RCGR
0x0011e4d0, // GCC_QUPV3_WRAP2_S4_CMD_RCGR
0x0011e600, // GCC_QUPV3_WRAP2_S5_CMD_RCGR
0x0010d00c, // GCC_RBCPR_MMCX_CMD_RCGR
0x00106038, // GCC_PCIE_2_AUX_CMD_RCGR
};
static const char *const sm8250_rcg_names[] = {
"GCC_USB30_PRIM_MASTER_CMD_RCGR",
"GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR",
"GCC_USB3_PRIM_PHY_AUX_CMD_RCGR",
"GCC_USB30_SEC_MASTER_CMD_RCGR",
"GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR",
"GCC_USB3_SEC_PHY_AUX_CMD_RCGR",
"GCC_SDCC2_APPS_CMD_RCGR",
"GCC_SDCC4_APPS_CMD_RCGR",
"GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR",
"GCC_QUPV3_WRAP0_S0_CMD_RCGR",
"GCC_QUPV3_WRAP0_S1_CMD_RCGR",
"GCC_QUPV3_WRAP0_S2_CMD_RCGR",
"GCC_QUPV3_WRAP0_S3_CMD_RCGR",
"GCC_QUPV3_WRAP0_S4_CMD_RCGR",
"GCC_QUPV3_WRAP0_S5_CMD_RCGR",
"GCC_QUPV3_WRAP0_S6_CMD_RCGR",
"GCC_QUPV3_WRAP0_S7_CMD_RCGR",
"GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR",
"GCC_QUPV3_WRAP1_S0_CMD_RCGR",
"GCC_QUPV3_WRAP1_S1_CMD_RCGR",
"GCC_QUPV3_WRAP1_S2_CMD_RCGR",
"GCC_QUPV3_WRAP1_S3_CMD_RCGR",
"GCC_QUPV3_WRAP1_S4_CMD_RCGR",
"GCC_QUPV3_WRAP1_S5_CMD_RCGR",
"GCC_PCIE_0_AUX_CMD_RCGR",
"GCC_PCIE_1_AUX_CMD_RCGR",
"GCC_PCIE_PHY_REFGEN_CMD_RCGR",
"GCC_UFS_CARD_AXI_CMD_RCGR",
"GCC_UFS_CARD_ICE_CORE_CMD_RCGR",
"GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR",
"GCC_UFS_CARD_PHY_AUX_CMD_RCGR",
"GCC_UFS_PHY_AXI_CMD_RCGR",
"GCC_UFS_PHY_ICE_CORE_CMD_RCGR",
"GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR",
"GCC_UFS_PHY_PHY_AUX_CMD_RCGR",
"GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR",
"GCC_QUPV3_WRAP2_S0_CMD_RCGR",
"GCC_QUPV3_WRAP2_S1_CMD_RCGR",
"GCC_QUPV3_WRAP2_S2_CMD_RCGR",
"GCC_QUPV3_WRAP2_S3_CMD_RCGR",
"GCC_QUPV3_WRAP2_S4_CMD_RCGR",
"GCC_QUPV3_WRAP2_S5_CMD_RCGR",
"GCC_RBCPR_MMCX_CMD_RCGR",
"GCC_PCIE_2_AUX_CMD_RCGR",
};
static struct msm_clk_data qcs404_gcc_data = {
.resets = sm8250_gcc_resets,
.num_resets = ARRAY_SIZE(sm8250_gcc_resets),
.clks = sm8250_clks,
.num_clks = ARRAY_SIZE(sm8250_clks),
.power_domains = sm8250_gdscs,
.num_power_domains = ARRAY_SIZE(sm8250_gdscs),
.enable = sm8250_enable,
.set_rate = sm8250_set_rate,
.dbg_pll_addrs = sm8250_gpll_addrs,
.num_plls = ARRAY_SIZE(sm8250_gpll_addrs),
.dbg_rcg_addrs = sm8250_rcg_addrs,
.num_rcgs = ARRAY_SIZE(sm8250_rcg_addrs),
.dbg_rcg_names = sm8250_rcg_names,
};
static const struct udevice_id gcc_sm8250_of_match[] = {
{
.compatible = "qcom,gcc-sm8250",
.data = (ulong)&qcs404_gcc_data,
},
{}
};
U_BOOT_DRIVER(gcc_sm8250) = {
.name = "gcc_sm8250",
.id = UCLASS_NOP,
.of_match = gcc_sm8250_of_match,
.bind = qcom_cc_bind,
.flags = DM_FLAG_PRE_RELOC,
};
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