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7c5460afec
If we try to enable a gate clock that doesn't exist, we used to just fail silently. This may make sense for early bringup of some core peripherals that we know are already enabled, but it only makes debugging missing clocks more difficult. Bubble up errors now that qcom_gate_clk_en() can return an error code to catch any still-missing clocks and make it easier to find missing ones as more complicated peripherals are enabled. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
141 lines
4.0 KiB
C
141 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock drivers for Qualcomm sa8775p
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*
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* (C) Copyright 2024 Linaro Ltd.
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*/
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#include <linux/types.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <linux/bug.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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#include "clock-qcom.h"
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#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
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#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
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static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id < priv->data->num_clks)
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debug("%s: %s, requested rate=%ld\n", __func__,
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priv->data->clks[clk->id].name, rate);
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switch (clk->id) {
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case GCC_USB30_PRIM_MOCK_UTMI_CLK:
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WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
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clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
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return rate;
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case GCC_USB30_PRIM_MASTER_CLK:
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WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
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clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
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1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
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clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
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return rate;
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default:
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return 0;
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}
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}
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static const struct gate_clk sa8775p_clks[] = {
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GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1),
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GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1),
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GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1),
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GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1),
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GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
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GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
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GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
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};
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static int sa8775p_enable(struct clk *clk)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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if (priv->data->num_clks < clk->id) {
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debug("%s: unknown clk id %lu\n", __func__, clk->id);
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return 0;
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}
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debug("%s: clk %ld: %s\n", __func__, clk->id, sa8775p_clks[clk->id].name);
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switch (clk->id) {
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case GCC_AGGRE_USB3_PRIM_AXI_CLK:
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qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
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fallthrough;
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case GCC_USB30_PRIM_MASTER_CLK:
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qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
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qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
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break;
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}
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return qcom_gate_clk_en(priv, clk->id);
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}
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static const struct qcom_reset_map sa8775p_gcc_resets[] = {
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[GCC_CAMERA_BCR] = { 0x32000 },
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[GCC_DISPLAY1_BCR] = { 0xC7000 },
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[GCC_DISPLAY_BCR] = { 0x33000 },
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[GCC_EMAC0_BCR] = { 0xB6000 },
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[GCC_EMAC1_BCR] = { 0xB4000 },
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[GCC_GPU_BCR] = { 0x7D000 },
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[GCC_MMSS_BCR] = { 0x17000 },
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[GCC_PCIE_0_BCR] = { 0xa9000 },
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[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xBF000 },
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[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xBF008 },
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[GCC_PCIE_0_PHY_BCR] = { 0xAD144 },
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[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xBF00C },
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[GCC_PCIE_1_BCR] = { 0x77000 },
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[GCC_PCIE_1_LINK_DOWN_BCR] = { 0xAE084 },
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[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xAE090 },
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[GCC_PCIE_1_PHY_BCR] = { 0xAE08C },
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[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xAE094 },
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[GCC_PDM_BCR] = { 0x3F000 },
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[GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
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[GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
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[GCC_QUPV3_WRAPPER_2_BCR] = { 0x2A000 },
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[GCC_QUPV3_WRAPPER_3_BCR] = { 0xC4000 },
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[GCC_SDCC1_BCR] = { 0x20000 },
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[GCC_TSCSS_BCR] = { 0x21000 },
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[GCC_UFS_CARD_BCR] = { 0x81000 },
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[GCC_UFS_PHY_BCR] = { 0x83000 },
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};
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static const struct qcom_power_map sa8775p_gdscs[] = {
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[UFS_PHY_GDSC] = { 0x83004 },
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[USB30_PRIM_GDSC] = { 0x1B004 },
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};
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static struct msm_clk_data sa8775_gcc_data = {
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.resets = sa8775p_gcc_resets,
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.num_resets = ARRAY_SIZE(sa8775p_gcc_resets),
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.clks = sa8775p_clks,
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.num_clks = ARRAY_SIZE(sa8775p_clks),
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.power_domains = sa8775p_gdscs,
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.num_power_domains = ARRAY_SIZE(sa8775p_gdscs),
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.enable = sa8775p_enable,
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.set_rate = sa8775p_set_rate,
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};
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static const struct udevice_id gcc_sa8775p_of_match[] = {
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{
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.compatible = "qcom,sa8775p-gcc",
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.data = (ulong)&sa8775_gcc_data,
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},
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{ }
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};
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U_BOOT_DRIVER(gcc_sa8775p) = {
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.name = "gcc_sa8775p",
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.id = UCLASS_NOP,
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.of_match = gcc_sa8775p_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
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};
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