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7c5460afec
If we try to enable a gate clock that doesn't exist, we used to just fail silently. This may make sense for early bringup of some core peripherals that we know are already enabled, but it only makes debugging missing clocks more difficult. Bubble up errors now that qcom_gate_clk_en() can return an error code to catch any still-missing clocks and make it easier to find missing ones as more complicated peripherals are enabled. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
191 lines
6.1 KiB
C
191 lines
6.1 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm qcm2290
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*
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* (C) Copyright 2024 Linaro Ltd.
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <linux/bug.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
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#include "clock-qcom.h"
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#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608
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#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c
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static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
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F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625),
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F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625),
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F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
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F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625),
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F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75),
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F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25),
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F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75),
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F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0),
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F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15),
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F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25),
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F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
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F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375),
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F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75),
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F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625),
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F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0),
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F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0),
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{}
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};
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static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
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F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
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F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
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F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0),
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F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
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F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
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F(202000000, CFG_CLK_SRC_GPLL7, 4, 0, 0), // 6.5, 1, 4
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{}
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};
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static const struct pll_vote_clk gpll7_clk = {
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.status = 0x7000,
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.status_bit = BIT(31),
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.ena_vote = 0x79000,
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.vote_bit = BIT(7),
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};
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static const struct gate_clk qcm2290_clks[] = {
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GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, 0x00000001),
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GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, 0x00000001),
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GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, 0x00000200),
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GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, 0x00000100),
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GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, 0x00000400),
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GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, 0x00000800),
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GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, 0x00001000),
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GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, 0x00002000),
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GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, 0x00004000),
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GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, 0x00008000),
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GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, 0x00000040),
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GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, 0x00000080),
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GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, 0x00000001),
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GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, 0x00000001),
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GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, 0x00000001),
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GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, 0x00000001),
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GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, 0x00000001),
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GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, 0x00000001),
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GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, 0x00000001),
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GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, 0x00000001),
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GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, 0x00000001),
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GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, 0x00000001),
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GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x9f000, 0x00000001),
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GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, 0x00000001),
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GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, 0x00000001),
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};
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static ulong qcm2290_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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const struct freq_tbl *freq;
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debug("%s: clk %s rate %lu\n", __func__, clk->dev->name, rate);
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switch (clk->id) {
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case GCC_QUPV3_WRAP0_S4_CLK: /*UART2*/
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freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
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clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR,
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freq->pre_div, freq->m, freq->n, freq->src,
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16);
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return 0;
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case GCC_SDCC2_APPS_CLK:
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/* Enable GPLL7 so we can point SDCC2_APPS_CLK_SRC RCG at it */
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clk_enable_gpll0(priv->base, &gpll7_clk);
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freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
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WARN(freq->src != CFG_CLK_SRC_GPLL7,
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"SDCC2_APPS_CLK_SRC not set to GPLL7, requested rate %lu\n",
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rate);
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clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
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freq->pre_div, freq->m, freq->n, freq->src,
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8);
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return freq->freq;
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case GCC_SDCC1_APPS_CLK:
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/* The firmware turns this on for us and always sets it to this rate */
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return 384000000;
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default:
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return 0;
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}
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}
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static int qcm2290_enable(struct clk *clk)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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if (priv->data->num_clks < clk->id) {
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debug("%s: unknown clk id %lu\n", __func__, clk->id);
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return 0;
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}
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debug("%s: clk %s\n", __func__, qcm2290_clks[clk->id].name);
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switch (clk->id) {
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case GCC_USB30_PRIM_MASTER_CLK:
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qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
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qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
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break;
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}
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return qcom_gate_clk_en(priv, clk->id);
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}
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static const struct qcom_reset_map qcm2290_gcc_resets[] = {
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[GCC_CAMSS_OPE_BCR] = { 0x55000 },
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[GCC_CAMSS_TFE_BCR] = { 0x52000 },
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[GCC_CAMSS_TOP_BCR] = { 0x58000 },
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[GCC_GPU_BCR] = { 0x36000 },
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[GCC_MMSS_BCR] = { 0x17000 },
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[GCC_PDM_BCR] = { 0x20000 },
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[GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
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[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
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[GCC_SDCC1_BCR] = { 0x38000 },
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[GCC_SDCC2_BCR] = { 0x1e000 },
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[GCC_USB30_PRIM_BCR] = { 0x1a000 },
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[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
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[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
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[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
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[GCC_VCODEC0_BCR] = { 0x58094 },
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[GCC_VENUS_BCR] = { 0x58078 },
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[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
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};
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static const struct qcom_power_map qcm2290_gdscs[] = {
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[GCC_USB30_PRIM_GDSC] = { 0x1a004 },
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};
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static struct msm_clk_data qcm2290_gcc_data = {
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.resets = qcm2290_gcc_resets,
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.num_resets = ARRAY_SIZE(qcm2290_gcc_resets),
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.clks = qcm2290_clks,
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.num_clks = ARRAY_SIZE(qcm2290_clks),
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.power_domains = qcm2290_gdscs,
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.num_power_domains = ARRAY_SIZE(qcm2290_gdscs),
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.enable = qcm2290_enable,
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.set_rate = qcm2290_set_rate,
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};
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static const struct udevice_id gcc_qcm2290_of_match[] = {
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{
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.compatible = "qcom,gcc-qcm2290",
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.data = (ulong)&qcm2290_gcc_data,
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},
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{}
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};
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U_BOOT_DRIVER(gcc_qcm2290) = {
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.name = "gcc_qcm2290",
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.id = UCLASS_NOP,
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.of_match = gcc_qcm2290_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC,
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};
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