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ad3e8a2f59
Add initial set of clocks and resets for enabling U-Boot on ipq9574 based RDP platforms. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250226064505.1178054-4-quic_varada@quicinc.com Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock drivers for Qualcomm ipq9574
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*
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* (C) Copyright 2025 Linaro Ltd.
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*/
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#include <linux/types.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <linux/bug.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
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#include "clock-qcom.h"
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#define GCC_BLSP1_AHB_CBCR 0x1004
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#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x402C
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#define GCC_BLSP1_UART3_APPS_CBCR 0x4054
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#define GCC_SDCC1_APPS_CBCR 0x3302C
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#define GCC_SDCC1_AHB_CBCR 0x33034
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#define GCC_SDCC1_APPS_CMD_RCGR 0x33004
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#define GCC_SDCC1_ICE_CORE_CBCR 0x33030
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static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case GCC_BLSP1_UART3_APPS_CLK:
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clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR,
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0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
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return rate;
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case GCC_SDCC1_APPS_CLK:
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clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
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11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
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return rate;
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default:
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return -EINVAL;
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}
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}
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static const struct gate_clk ipq9574_clks[] = {
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GATE_CLK(GCC_BLSP1_UART3_APPS_CLK, 0x4054, 0x00000001),
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GATE_CLK(GCC_BLSP1_AHB_CLK, 0x1004, 0x00000001),
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GATE_CLK(GCC_SDCC1_AHB_CLK, 0x33034, 0x00000001),
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GATE_CLK(GCC_SDCC1_APPS_CLK, 0x3302C, 0x00000001),
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GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x33030, 0x00000001),
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};
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static int ipq9574_enable(struct clk *clk)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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debug("%s: clk %s\n", __func__, ipq9574_clks[clk->id].name);
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if (!ipq9574_clks[clk->id].reg)
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return -EINVAL;
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qcom_gate_clk_en(priv, clk->id);
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return 0;
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}
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static const struct qcom_reset_map ipq9574_gcc_resets[] = {
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[GCC_SDCC_BCR] = { 0x33000 },
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};
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static struct msm_clk_data ipq9574_gcc_data = {
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.resets = ipq9574_gcc_resets,
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.num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
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.enable = ipq9574_enable,
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.set_rate = ipq9574_set_rate,
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};
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static const struct udevice_id gcc_ipq9574_of_match[] = {
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{
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.compatible = "qcom,ipq9574-gcc",
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.data = (ulong)&ipq9574_gcc_data,
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},
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{ }
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};
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U_BOOT_DRIVER(gcc_ipq9574) = {
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.name = "gcc_ipq9574",
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.id = UCLASS_NOP,
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.of_match = gcc_ipq9574_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
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};
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