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https://source.denx.de/u-boot/u-boot.git
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5d82183d4a
Use clock-names property which is accessible via parent clock OF node to look up the parent clock by name instead of depending on unreliable global clock name to perform look up. Signed-off-by: Marek Vasut <marex@denx.de>
130 lines
2.7 KiB
C
130 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Gated clock implementation
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*
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*/
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <linux/bug.h>
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#include <linux/clk-provider.h>
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#include <clk.h>
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#include "clk.h"
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#include <linux/err.h>
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#define UBOOT_DM_CLK_IMX_GATE2 "imx_clk_gate2"
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struct clk_gate2 {
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struct clk clk;
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void __iomem *reg;
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u8 bit_idx;
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u8 cgr_val;
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u8 flags;
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unsigned int *share_count;
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};
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#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
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static int clk_gate2_enable(struct clk *clk)
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{
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struct clk_gate2 *gate = to_clk_gate2(clk);
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u32 reg;
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if (gate->share_count && (*gate->share_count)++ > 0)
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return 0;
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reg = readl(gate->reg);
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reg &= ~(3 << gate->bit_idx);
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reg |= gate->cgr_val << gate->bit_idx;
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writel(reg, gate->reg);
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return 0;
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}
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static int clk_gate2_disable(struct clk *clk)
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{
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struct clk_gate2 *gate = to_clk_gate2(clk);
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u32 reg;
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if (gate->share_count) {
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if (WARN_ON(*gate->share_count == 0))
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return 0;
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else if (--(*gate->share_count) > 0)
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return 0;
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}
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reg = readl(gate->reg);
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reg &= ~(3 << gate->bit_idx);
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writel(reg, gate->reg);
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return 0;
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}
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static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)
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{
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struct clk *parent = clk_get_parent(clk);
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if (parent)
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return clk_set_rate(parent, rate);
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return -ENODEV;
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}
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static const struct clk_ops clk_gate2_ops = {
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.set_rate = clk_gate2_set_rate,
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.enable = clk_gate2_enable,
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.disable = clk_gate2_disable,
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.get_rate = clk_generic_get_rate,
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};
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struct clk *clk_register_gate2(struct udevice *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate2_flags, unsigned int *share_count)
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{
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struct clk_gate2 *gate;
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struct clk *clk;
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int ret;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->cgr_val = cgr_val;
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gate->flags = clk_gate2_flags;
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gate->share_count = share_count;
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clk = &gate->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name,
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clk_resolve_parent_clk(dev, parent_name));
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if (ret) {
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kfree(gate);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(clk_gate2) = {
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.name = UBOOT_DM_CLK_IMX_GATE2,
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.id = UCLASS_CLK,
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.ops = &clk_gate2_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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