Alif Zakuan Yuslaimi 58ef50ff9a drivers: clk: agilex5: Set PLL to asynchronous mode ... PLL frequency would overshoot from the original target in synchronous mode during low VCC voltage condition. To resolve this issue, PLL is set to run on asynchronous mode instead of enabling synchronous mode in the clock driver. Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>		2025-02-25 10:53:41 -06:00
..
clk-agilex5.c	drivers: clk: agilex5: Set PLL to asynchronous mode	2025-02-25 10:53:41 -06:00
clk-agilex5.h	arch: arm: Agilex5 enablement	2024-03-18 14:45:47 +08:00
clk-agilex.c	drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD	2024-10-11 11:44:48 -06:00
clk-agilex.h	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00
clk-arria10.c	Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"	2024-05-20 13:35:03 -06:00
clk-mem-n5x.c	Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"	2024-05-20 13:35:03 -06:00
clk-mem-n5x.h	clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)	2024-01-22 16:51:17 +08:00
clk-n5x.c	drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD	2024-10-11 11:44:48 -06:00
clk-n5x.h	drivers: clk: Update license for Intel N5X device	2022-07-01 15:00:39 +08:00
Makefile	arch: arm: Agilex5 enablement	2024-03-18 14:45:47 +08:00