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The Cadence NAND is a configurable mtd raw block which supports multiple options for chipsets, clocking and reset structure, and feature list. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> |
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.. | ||
spi | ||
altera_qspi.txt | ||
cadence,nand.yaml | ||
mtd-physmap.txt | ||
spi-nand.txt | ||
ti,elm.yaml | ||
ti,gpmc-nand.yaml |