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dde53eae88
Add support for the Toradex SMARC iMX8MP. Link: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx-8m-plus Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
117 lines
3.1 KiB
ReStructuredText
117 lines
3.1 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0-or-later
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Toradex SMARC iMX8M Plus Module
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===============================
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- SoM: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx-8m-plus
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- Carrier board: https://www.toradex.com/products/carrier-board/smarc-development-board-kit
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Quick Start
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-----------
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- Build the ARM trusted firmware binary
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- Get the DDR firmware
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- Build U-Boot
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- Flash to eMMC
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- Boot
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Get and Build the ARM Trusted Firmware (Trusted Firmware A)
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-----------------------------------------------------------
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.. code-block:: bash
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$ echo "Downloading and building TF-A..."
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$ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
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$ cd trusted-firmware-a
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Then build ATF (TF-A):
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.. code-block:: bash
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$ export CROSS_COMPILE=aarch64-linux-gnu-
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$ make PLAT=imx8mp IMX_BOOT_UART_BASE=0x30a60000 bl31
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$ cp build/imx8mp/release/bl31.bin ../
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Get the DDR Firmware
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--------------------
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.. code-block:: bash
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$ cd ..
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.1.bin
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$ chmod +x firmware-imx-8.10.1.bin
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$ ./firmware-imx-8.10.1.bin
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$ cp firmware-imx-8.10.1/firmware/ddr/synopsys/lpddr4*_202006.bin ./
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Build U-Boot
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------------
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.. code-block:: bash
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$ export CROSS_COMPILE=aarch64-linux-gnu-
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$ make toradex-smarc-imx8mp_defconfig
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$ make
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Flash to eMMC
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-------------
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.. code-block:: bash
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> tftpboot ${loadaddr} flash.bin
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> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
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> mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt}
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As a convenience, instead of the last two commands, one may also use the update
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U-Boot wrapper:
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.. code-block:: bash
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> run update_uboot
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Boot
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----
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ATF, U-Boot proper and u-boot.dtb images are packed into a FIT image,
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which is loaded and parsed by SPL.
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Boot sequence is:
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* SPL ---> ATF (TF-A) ---> U-Boot proper
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Output::
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U-Boot SPL 2025.04-rc5-00023-g34c31be81211 (Apr 04 2025 - 15:36:23 +0100)
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Training FAILED
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DDR configured as single rank
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SEC0: RNG instantiated
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Normal Boot
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Trying to boot from BOOTROM
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Boot Stage: Primary boot
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Find img info 0x4802f200, size 1100
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Need continue download 1024
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NOTICE: Do not release JR0 to NS as it can be used by HAB
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NOTICE: BL31: v2.11.0(release):v2.11.0-723-gbd298f5c30ac
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NOTICE: BL31: Built : 14:18:43, Apr 4 2025
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U-Boot 2025.04-rc5-00023-g34c31be81211 (Apr 04 2025 - 15:36:23 +0100)
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CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
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CPU: Industrial temperature grade (-40C to 105C) at 72C
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Reset cause: POR
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DRAM: 4 GiB
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Core: 312 devices, 32 uclasses, devicetree: separate
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WDT: Started watchdog@30280000 with servicing every 1000ms (60s timeout)
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MMC: FSL_SDHC: 1, FSL_SDHC: 0
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Loading Environment from MMC... Reading from MMC(0)... OK
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In: serial@30a60000
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Out: serial@30a60000
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Err: serial@30a60000
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Model: Toradex 0097 SMARC iMX8M Plus Quad 4GB WB IT V1.0A
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Serial#: 15603364
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SEC0: RNG instantiated
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Net: Get shared mii bus on ethernet@30be0000
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eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
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Hit any key to stop autoboot: 0
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SMARC iMX8MP #
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