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AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
86 lines
1.4 KiB
C
86 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#include <asm/io.h>
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#include <asm/arch/sli.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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int ret;
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struct udevice *dev;
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struct ram_info ram;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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printf("cannot get DRAM driver\n");
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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printf("cannot get DRAM information\n");
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return ret;
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}
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gd->ram_size = ram.size;
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return 0;
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}
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int spl_board_init_f(void)
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{
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sli_init();
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dram_init();
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return 0;
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}
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struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
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{
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return (struct legacy_img_hdr *)CONFIG_SYS_LOAD_ADDR;
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}
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void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
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{
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return (void *)spl_get_load_buffer(sectors, bl_len);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_RAM;
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}
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int board_init(void)
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{
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struct udevice *dev;
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int i = 0;
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int ret;
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/*
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* Loop over all MISC uclass drivers to call the comphy code
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* and init all CP110 devices enabled in the DT
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*/
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while (1) {
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/* Call the comphy code via the MISC uclass driver */
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ret = uclass_get_device(UCLASS_MISC, i++, &dev);
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/* We're done, once no further CP110 device is found */
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if (ret)
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break;
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}
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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