Minda Chen 05aa34cef9 spl: starfive: visionfive2: Disable USB overcurrent pin by default. ... For some JH7110 boards, USB host overcurent pin is not reserved, To make USB host work, overcurrent pin must be disabled. So set the pin default disabled in spl stage. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Tested-by: E Shattow <lucent@gmail.com>		2025-03-17 01:55:19 +01:00
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arch-andes	andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND	2024-05-30 16:01:13 +08:00
arch-ast2700	ram: ast2700: Add DRAM controller initialization	2024-09-11 20:35:03 +08:00
arch-fu540	board: sifive: Rename spl_soc_init() to spl_dram_init()	2024-05-02 00:01:18 +08:00
arch-fu740	board: sifive: Rename spl_soc_init() to spl_dram_init()	2024-05-02 00:01:18 +08:00
arch-generic	dm: treewide: Rename ..._platdata variables to just ..._plat	2020-12-13 16:51:09 -07:00
arch-jh7110	spl: starfive: visionfive2: Disable USB overcurrent pin by default.	2025-03-17 01:55:19 +01:00
acpi_table.h	acpi: Add missing RISC-V acpi_table header	2023-08-02 11:02:33 +08:00
asm.h	riscv: Sync csr.h with Linux kernel v5.2	2019-08-15 13:42:28 +08:00
atomic.h	riscv: add generic link for <asm/atomic.h>	2023-07-06 17:28:08 +08:00
barrier.h	riscv: make use of the barrier functions from Linux	2018-11-26 13:57:30 +08:00
bitops.h	riscv: define find_{first,next}_zero_bit in asm/bitops.h	2024-09-10 10:10:43 +08:00
byteorder.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00
cache.h	riscv: lib: modify the indent	2021-09-07 10:34:29 +08:00
config.h	Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig	2022-07-07 14:01:09 -04:00
cpufeature.h	riscv: Enhance extension probing	2025-01-16 15:34:18 +08:00
csr.h	andes: csr.h: Clean up CSR definition	2023-12-27 17:29:07 +08:00
dma-mapping.h	riscv: Remove common.h usage	2023-10-24 16:34:45 -04:00
encoding.h	global: Finish CONFIG -> CFG migration	2023-01-20 12:27:24 -05:00
global_data.h	riscv: resume needs to be a global	2024-10-29 19:58:14 +08:00
gpio.h	gpio: sifive: add support for DM based gpio driver for FU540-SoC	2019-10-18 09:04:01 +08:00
hwcap.h	riscv: Enhance extension probing	2025-01-16 15:34:18 +08:00
insn-def.h	riscv: Add support for defining instructions	2024-10-28 18:56:54 +08:00
io.h	riscv: io.h: Fix signatures of reads/writes functions	2023-11-28 16:19:06 -05:00
linkage.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
posix_types.h	riscv: fix use of incorrectly sized variables	2018-11-26 13:57:29 +08:00
processor.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00
ptrace.h	riscv: checkpatch: Fix alignment should match open parenthesis	2018-03-30 13:13:22 +08:00
sbi.h	cmd: sbi: Add FWFT, MPXY extensions	2024-10-28 16:11:33 +08:00
sections.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
setjmp.h	common: clean up setjmp.h	2025-03-10 07:41:16 +01:00
smp.h	riscv: Remove common.h usage	2023-10-24 16:34:45 -04:00
spl.h	common: spl: Add spl NVMe boot support	2023-06-19 17:47:41 -04:00
string.h	riscv: Add Zbb support for building U-Boot	2023-10-19 17:29:50 +08:00
syscon.h	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
system.h	event: Convert existing spy records to simple	2023-08-31 13:16:54 -04:00
types.h	riscv: Change phys_addr_t and phys_size_t to 64-bit	2021-02-03 03:38:41 -07:00
u-boot-riscv.h	riscv: Provide a mechanism to fix DT for reserved memory	2020-04-23 10:14:16 +08:00
u-boot.h	bdinfo: riscv: Use generic bd_info	2020-06-25 13:24:10 -04:00
unaligned.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00