Venkatesh Yadav Abbarapu 5b8d6dcf7c ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers ... Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly read/write to the pmc_iou_slcr and efuse_cache registers. Replace these raw reads/writes with the xilinx_pm_request() API with the correct arguments once the PM related changes are done. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com		2025-04-16 13:42:06 +02:00
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hardware.h	ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers	2025-04-16 13:42:06 +02:00
sys_proto.h	arm64: versal2: Add support for AMD Versal Gen 2	2024-06-17 16:02:29 +02:00