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cf5b58ef6e
Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as FPGA2SoC and SoC2FPGA bridges for all SoC64 families. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
86 lines
3.4 KiB
C
86 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
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*/
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#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
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#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#define SOCFPGA_CCU_ADDRESS 0x1c000000
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#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000
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#define SOCFPGA_SMMU_ADDRESS 0x16000000
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#define SOCFPGA_OCRAM_FIREWALL_ADDRESS 0x108cc400
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#define SOCFPGA_MAILBOX_ADDRESS 0x10a30000
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#define SOCFPGA_UART0_ADDRESS 0x10c02000
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#define SOCFPGA_UART1_ADDRESS 0x10c02100
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#define SOCFPGA_SPTIMER0_ADDRESS 0x10c03000
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#define SOCFPGA_SPTIMER1_ADDRESS 0x10c03100
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#define SOCFPGA_SYSTIMER0_ADDRESS 0x10d00000
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#define SOCFPGA_SYSTIMER1_ADDRESS 0x10d00100
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#define SOCFPGA_L4WD0_ADDRESS 0x10d00200
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#define SOCFPGA_L4WD1_ADDRESS 0x10d00300
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#define SOCFPGA_L4WD2_ADDRESS 0x10d00400
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#define SOCFPGA_L4WD3_ADDRESS 0x10d00500
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#define SOCFPGA_L4WD4_ADDRESS 0x10d00600
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#define SOCFPGA_GTIMER_SEC_ADDRESS 0x10d01000
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#define SOCFPGA_GTIMER_NSEC_ADDRESS 0x10d02000
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#define SOCFPGA_CLKMGR_ADDRESS 0x10d10000
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#define SOCFPGA_RSTMGR_ADDRESS 0x10d11000
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#define SOCFPGA_SYSMGR_ADDRESS 0x10d12000
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#define SOCFPGA_OCRAM_ADDRESS 0x00000000
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#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800
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#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00
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#define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00
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#define SOCFPGA_FIREWALL_L4_PER 0x10d21000
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#define SOCFPGA_FIREWALL_L4_SYS 0x10d21100
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#define SOCFPGA_FIREWALL_SOC2FPGA 0x10d21200
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#define SOCFPGA_FIREWALL_LWSOC2FPGA 0x10d21300
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#define SOCFPGA_FIREWALL_TCU 0x10d21400
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#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0x10d24800
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#define GICD_BASE 0x1d000000
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#define GICR_BASE 0x1d060000
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#else
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#define SOCFPGA_CCU_ADDRESS 0xf7000000
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#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
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#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
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#define SOCFPGA_SDR_ADDRESS 0xf8011000
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
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IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200
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#else
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#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
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#endif
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#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000
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#define SOCFPGA_SMMU_ADDRESS 0xfa000000
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#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
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#define SOCFPGA_UART0_ADDRESS 0xffc02000
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#define SOCFPGA_UART1_ADDRESS 0xffc02100
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#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
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#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
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#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
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#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
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#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
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#define SOCFPGA_L4WD1_ADDRESS 0xffd00300
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#define SOCFPGA_L4WD2_ADDRESS 0xffd00400
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#define SOCFPGA_L4WD3_ADDRESS 0xffd00500
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#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
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#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
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#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
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#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
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#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
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#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
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#define SOCFPGA_FIREWALL_L4_PER 0xffd21000
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#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100
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#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200
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#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300
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#define SOCFPGA_FIREWALL_TCU 0xffd21400
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#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
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#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
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#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
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#define GICD_BASE 0xfffc1000
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#define GICC_BASE 0xfffc2000
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#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */
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#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
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