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b396583c58
Vendor Authorized Boot flow configurations are enabled for boards based on Agilex5 SoCFPGA. Also, required changes are made to the SoCFPGA make file for building and linking relevant secure source code files. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
130 lines
3.2 KiB
Makefile
130 lines
3.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
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# Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
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obj-y += board.o
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obj-y += clock_manager.o
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obj-y += misc.o
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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obj-y += clock_manager_gen5.o
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obj-y += misc_gen5.o
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obj-y += reset_manager_gen5.o
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obj-y += scan_manager.o
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obj-y += system_manager_gen5.o
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obj-y += timer.o
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obj-y += wrap_pll_config.o
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obj-y += fpga_manager.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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obj-y += clock_manager_arria10.o
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obj-y += misc_arria10.o
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obj-y += pinmux_arria10.o
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obj-y += reset_manager_arria10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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obj-y += clock_manager_s10.o
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obj-y += lowlevel_init_soc64.o
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obj-y += mailbox_s10.o
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obj-y += misc_soc64.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-y += system_manager_soc64.o
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obj-y += timer_s10.o
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obj-y += wrap_handoff_soc64.o
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obj-y += wrap_pll_config_soc64.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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obj-y += clock_manager_agilex.o
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obj-y += lowlevel_init_soc64.o
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obj-y += mailbox_s10.o
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obj-y += misc_soc64.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
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obj-y += system_manager_soc64.o
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obj-y += timer_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
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obj-y += wrap_handoff_soc64.o
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obj-y += wrap_pll_config_soc64.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
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obj-y += clock_manager_agilex5.o
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obj-y += mailbox_s10.o
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obj-y += misc_soc64.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-y += wrap_handoff_soc64.o
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obj-y += wrap_pll_config_soc64.o
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obj-y += altera-sysmgr.o
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obj-y += ccu_ncore3.o
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obj-y += system_manager_soc64.o
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obj-y += timer_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_N5X
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obj-y += clock_manager_n5x.o
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obj-y += lowlevel_init_soc64.o
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obj-y += mailbox_s10.o
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obj-y += misc_soc64.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
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obj-y += system_manager_soc64.o
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obj-y += timer_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
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obj-y += wrap_handoff_soc64.o
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obj-y += wrap_pll_config_soc64.o
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endif
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ifdef CONFIG_XPL_BUILD
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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obj-y += spl_gen5.o
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obj-y += freeze_controller.o
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obj-y += wrap_iocsr_config.o
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obj-y += wrap_pinmux_config.o
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obj-y += wrap_sdram_config.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_SOC64
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obj-y += firewall.o
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obj-y += spl_soc64.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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obj-y += spl_a10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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obj-y += spl_s10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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obj-y += spl_agilex.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_N5X
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obj-y += spl_n5x.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
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obj-y += spl_soc64.o
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obj-y += spl_agilex5.o
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endif
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else
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obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
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obj-$(CONFIG_SPL_ATF) += smc_api.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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# QTS-generated config file wrappers
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CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
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endif
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