mirror of
https://source.denx.de/u-boot/u-boot.git
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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
559 lines
16 KiB
C
559 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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* Contact: Greg Malysa <greg.malysa@timesys.com>
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*/
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#include <asm/arch-adi/sc5xx/sc5xx.h>
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#include <asm/io.h>
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#include <linux/types.h>
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#include "clkinit.h"
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#include "dmcinit.h"
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#ifdef CONFIG_CGU0_SCLK0_DIV
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#define VAL_CGU0_SCLK0_DIV CONFIG_CGU0_SCLK0_DIV
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#else
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#define VAL_CGU0_SCLK0_DIV 1
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#endif
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#ifdef CONFIG_CGU0_SCLK1_DIV
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#define VAL_CGU0_SCLK1_DIV CONFIG_CGU0_SCLK1_DIV
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#else
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#define VAL_CGU0_SCLK1_DIV 1
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#endif
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#ifdef CONFIG_CGU0_DIV_S0SELEX
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#define VAL_CGU0_DIV_S0SELEX CONFIG_CGU0_DIV_S0SELEX
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#else
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#define VAL_CGU0_DIV_S0SELEX -1
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#endif
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#ifdef CONFIG_CGU0_DIV_S1SELEX
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#define VAL_CGU0_DIV_S1SELEX CONFIG_CGU0_DIV_S1SELEX
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#else
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#define VAL_CGU0_DIV_S1SELEX -1
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#endif
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#ifdef CONFIG_CGU0_CLKOUTSEL
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#define VAL_CGU0_CLKOUTSEL CONFIG_CGU0_CLKOUTSEL
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#else
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#define VAL_CGU0_CLKOUTSEL -1
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#endif
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#ifdef CONFIG_CGU1_SCLK0_DIV
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#define VAL_CGU1_SCLK0_DIV CONFIG_CGU1_SCLK0_DIV
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#else
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#define VAL_CGU1_SCLK0_DIV 1
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#endif
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#ifdef CONFIG_CGU1_SCLK1_DIV
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#define VAL_CGU1_SCLK1_DIV CONFIG_CGU1_SCLK1_DIV
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#else
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#define VAL_CGU1_SCLK1_DIV 1
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#endif
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#ifdef CONFIG_CGU1_DIV_S0SELEX
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#define VAL_CGU1_DIV_S0SELEX CONFIG_CGU1_DIV_S0SELEX
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#else
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#define VAL_CGU1_DIV_S0SELEX -1
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#endif
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#ifdef CONFIG_CGU1_DIV_S1SELEX
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#define VAL_CGU1_DIV_S1SELEX CONFIG_CGU1_DIV_S1SELEX
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#else
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#define VAL_CGU1_DIV_S1SELEX -1
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#endif
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#ifdef CONFIG_CGU1_CLKOUTSEL
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#define VAL_CGU1_CLKOUTSEL CONFIG_CGU1_CLKOUTSEL
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#else
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#define VAL_CGU1_CLKOUTSEL -1
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#endif
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#define REG_MISC_REG10_tst_addr 0x310A902C
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#define CGU0_REGBASE 0x3108D000
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#define CGU1_REGBASE 0x3108E000
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#define CGU_CTL 0x00 // CGU0 Control Register
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#define CGU_PLLCTL 0x04 // CGU0 PLL Control Register
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#define CGU_STAT 0x08 // CGU0 Status Register
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#define CGU_DIV 0x0C // CGU0 Clocks Divisor Register
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#define CGU_CLKOUTSEL 0x10 // CGU0 CLKOUT Select Register
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#define CGU_DIVEX 0x40 // CGU0 DIV Register Extension
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#define BITP_CGU_DIV_OSEL 22 // OUTCLK Divisor
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#define BITP_CGU_DIV_DSEL 16 // DCLK Divisor
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#define BITP_CGU_DIV_S1SEL 13 // SCLK 1 Divisor
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#define BITP_CGU_DIV_SYSSEL 8 // SYSCLK Divisor
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#define BITP_CGU_DIV_S0SEL 5 // SCLK 0 Divisor
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#define BITP_CGU_DIV_CSEL 0 // CCLK Divisor
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#define BITP_CGU_CTL_MSEL 8 // Multiplier Select
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#define BITP_CGU_CTL_DF 0 // Divide Frequency
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#define BITM_CGU_STAT_CLKSALGN 0x00000008
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#define BITM_CGU_STAT_PLOCK 0x00000004
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#define BITM_CGU_STAT_PLLBP 0x00000002
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#define BITM_CGU_STAT_PLLEN 0x00000001
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/* PLL Multiplier and Divisor Selections (Required Value, Bit Position) */
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/* PLL Multiplier Select */
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#define MSEL(X) (((X) << BITP_CGU_CTL_MSEL) & \
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BITM_CGU_CTL_MSEL)
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/* Divide frequency[true or false] */
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#define DF(X) (((X) << BITP_CGU_CTL_DF) & \
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BITM_CGU_CTL_DF)
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/* Core Clock Divisor Select */
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#define CSEL(X) (((X) << BITP_CGU_DIV_CSEL) & \
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BITM_CGU_DIV_CSEL)
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/* System Clock Divisor Select */
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#define SYSSEL(X) (((X) << BITP_CGU_DIV_SYSSEL) & \
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BITM_CGU_DIV_SYSSEL)
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/* SCLK0 Divisor Select */
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#define S0SEL(X) (((X) << BITP_CGU_DIV_S0SEL) & \
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BITM_CGU_DIV_S0SEL)
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/* SCLK1 Divisor Select */
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#define S1SEL(X) (((X) << BITP_CGU_DIV_S1SEL) & \
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BITM_CGU_DIV_S1SEL)
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/* DDR Clock Divisor Select */
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#define DSEL(X) (((X) << BITP_CGU_DIV_DSEL) & \
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BITM_CGU_DIV_DSEL)
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/* OUTCLK Divisor Select */
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#define OSEL(X) (((X) << BITP_CGU_DIV_OSEL) & \
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BITM_CGU_DIV_OSEL)
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/* CLKOUT select */
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#define CLKOUTSEL(X) (((X) << BITP_CGU_CLKOUTSEL_CLKOUTSEL) & \
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BITM_CGU_CLKOUTSEL_CLKOUTSEL)
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#define S0SELEX(X) (((X) << BITP_CGU_DIVEX_S0SELEX) & \
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BITM_CGU_DIVEX_S0SELEX)
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#define S1SELEX(X) (((X) << BITP_CGU_DIVEX_S1SELEX) & \
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BITM_CGU_DIVEX_S1SELEX)
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struct CGU_Settings {
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phys_addr_t rbase;
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u32 ctl_MSEL:7;
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u32 ctl_DF:1;
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u32 div_CSEL:5;
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u32 div_SYSSEL:5;
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u32 div_S0SEL:3;
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u32 div_S1SEL:3;
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u32 div_DSEL:5;
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u32 div_OSEL:7;
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s16 divex_S0SELEX;
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s16 divex_S1SELEX;
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s8 clkoutsel;
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};
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/* CGU Registers */
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#define BITM_CGU_CTL_LOCK 0x80000000 /* Lock */
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#define BITM_CGU_CTL_MSEL 0x00007F00 /* Multiplier Select */
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#define BITM_CGU_CTL_DF 0x00000001 /* Divide Frequency */
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#define BITM_CGU_CTL_S1SELEXEN 0x00020000 /* SCLK1 Extension Divider Enable */
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#define BITM_CGU_CTL_S0SELEXEN 0x00010000 /* SCLK0 Extension Divider Enable */
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#define BITM_CGU_DIV_LOCK 0x80000000 /* Lock */
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#define BITM_CGU_DIV_UPDT 0x40000000 /* Update Clock Divisors */
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#define BITM_CGU_DIV_ALGN 0x20000000 /* Align */
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#define BITM_CGU_DIV_OSEL 0x1FC00000 /* OUTCLK Divisor */
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#define BITM_CGU_DIV_DSEL 0x001F0000 /* DCLK Divisor */
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#define BITM_CGU_DIV_S1SEL 0x0000E000 /* SCLK 1 Divisor */
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#define BITM_CGU_DIV_SYSSEL 0x00001F00 /* SYSCLK Divisor */
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#define BITM_CGU_DIV_S0SEL 0x000000E0 /* SCLK 0 Divisor */
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#define BITM_CGU_DIV_CSEL 0x0000001F /* CCLK Divisor */
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#define BITP_CGU_DIVEX_S0SELEX 0
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#define BITM_CGU_DIVEX_S0SELEX 0x000000FF /* SCLK 0 Extension Divisor */
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#define BITP_CGU_DIVEX_S1SELEX 16
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#define BITM_CGU_DIVEX_S1SELEX 0x00FF0000 /* SCLK 1 Extension Divisor */
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#define BITM_CGU_PLLCTL_PLLEN 0x00000008 /* PLL Enable */
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#define BITM_CGU_PLLCTL_PLLBPCL 0x00000002 /* PLL Bypass Clear */
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#define BITM_CGU_PLLCTL_PLLBPST 0x00000001 /* PLL Bypass Set */
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#define BITP_CGU_CLKOUTSEL_CLKOUTSEL 0 /* CLKOUT Select */
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#define BITM_CGU_CLKOUTSEL_CLKOUTSEL 0x0000001F /* CLKOUT Select */
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#define CGU_STAT_MASK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK | \
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BITM_CGU_STAT_CLKSALGN)
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#define CGU_STAT_ALGN_LOCK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK)
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/* Clock Distribution Unit Registers */
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#define REG_CDU0_CFG0 0x3108F000
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#define REG_CDU0_CFG1 0x3108F004
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#define REG_CDU0_CFG2 0x3108F008
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#define REG_CDU0_CFG3 0x3108F00C
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#define REG_CDU0_CFG4 0x3108F010
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#define REG_CDU0_CFG5 0x3108F014
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#define REG_CDU0_CFG6 0x3108F018
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#define REG_CDU0_CFG7 0x3108F01C
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#define REG_CDU0_CFG8 0x3108F020
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#define REG_CDU0_CFG9 0x3108F024
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#define REG_CDU0_CFG10 0x3108F028
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#define REG_CDU0_CFG11 0x3108F02C
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#define REG_CDU0_CFG12 0x3108F030
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#define REG_CDU0_CFG13 0x3108F034
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#define REG_CDU0_CFG14 0x3108F038
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#define REG_CDU0_STAT 0x3108F040
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#define REG_CDU0_CLKINSEL 0x3108F044
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#define REG_CDU0_REVID 0x3108F048
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#define BITM_REG10_MSEL3 0x000007F0
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#define BITP_REG10_MSEL3 4
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#define BITM_REG10_DSEL3 0x0001F000
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#define BITP_REG10_DSEL3 12
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/* Selected clock macros */
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#define CGUn_MULT(cgu) ((CONFIG_CGU##cgu##_VCO_MULT == 0) ? \
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128 : CONFIG_CGU##cgu##_VCO_MULT)
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#define CGUn_DIV(clkname, cgu) ((CONFIG_CGU##cgu##_##clkname##_DIV == 0) ? \
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32 : CONFIG_CGU##cgu##_##clkname##_DIV)
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#define CCLK1_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \
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(1 + CONFIG_CGU##cgu##_DF_DIV)) / \
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CGUn_DIV(CCLK, cgu))
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#define CCLK2_n_RATIO(cgu) (((CGUn_MULT(cgu) * 2) / 3) / \
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(1 + CONFIG_CGU##cgu##_DF_DIV))
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#define DCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \
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(1 + CONFIG_CGU##cgu##_DF_DIV)) / \
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CGUn_DIV(DCLK, cgu))
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#define SYSCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \
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(1 + CONFIG_CGU##cgu##_DF_DIV)) / \
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CGUn_DIV(SCLK, cgu))
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#define PLL3_RATIO ((CONFIG_CGU1_PLL3_VCO_MSEL) / \
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(CONFIG_CGU1_PLL3_DCLK_DIV))
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#if (1 == CONFIG_CDU0_CLKO2)
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#define ARMCLK_IN 0
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#define ARMCLK_RATIO CCLK1_n_RATIO(0)
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#elif (3 == CONFIG_CDU0_CLKO2) && \
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(defined(CONFIG_SC57X) || defined(CONFIG_SC58X))
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#define ARMCLK_IN 0
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#define ARMCLK_RATIO SYSCLK_n_RATIO(0)
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#elif (5 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64)
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#define ARMCLK_IN 0
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#define ARMCLK_RATIO CCLK2_n_RATIO(0)
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#elif (7 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64)
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#define ARMCLK_IN CDU0_CGU1_CLKIN
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#define ARMCLK_RATIO CCLK2_n_RATIO(1)
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#endif
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#ifdef CONFIG_CGU1_PLL3_DDRCLK
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#define DDRCLK_IN CDU0_CGU1_CLKIN
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#define DDRCLK_RATIO PLL3_RATIO
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#elif (1 == CONFIG_CDU0_CLKO3)
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#define DDRCLK_IN 0
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#define DDRCLK_RATIO DCLK_n_RATIO(0)
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#elif (3 == CONFIG_CDU0_CLKO3)
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#define DDRCLK_IN CDU0_CGU1_CLKIN
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#define DDRCLK_RATIO DCLK_n_RATIO(1)
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#endif
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#ifndef ARMCLK_RATIO
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#error Invalid/unknown ARMCLK selection!
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#endif
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#ifndef DDRCLK_RATIO
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#error Invalid/unknown DDRCLK selection!
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#endif
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#define ARMDDR_CLK_RATIO_FPERCISION 1000
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#if ARMCLK_IN != DDRCLK_IN
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#ifndef CUSTOM_ARMDDR_CLK_RATIO
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/**
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* SYS_CLKINx are defined within the device tree, not configs.
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* Thus, we can only determine cross-CGU clock ratios if they
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* use the same SYS_CLKINx.
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*/
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#error Define CUSTOM_ARMDDR_CLK_RATIO for different SYS_CLKINs
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#else
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#define ARMDDR_CLK_RATIO CUSTOM_ARMDDR_CLK_RATIO
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#endif
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#else
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#define ARMDDR_CLK_RATIO (ARMDDR_CLK_RATIO_FPERCISION *\
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ARMCLK_RATIO / DDRCLK_RATIO)
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#endif
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void dmcdelay(uint32_t delay)
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{
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/* There is no zero-overhead loop on ARM, so assume each iteration
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* takes 4 processor cycles (based on examination of -O3 and -Ofast
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* output).
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*/
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u32 i, remainder;
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/* Convert DDR cycles to core clock cycles */
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u32 f = delay * ARMDDR_CLK_RATIO;
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delay = f + 500;
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delay /= ARMDDR_CLK_RATIO_FPERCISION;
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/* Round up to multiple of 4 */
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remainder = delay % 4;
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if (remainder != 0u)
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delay += (4u - remainder);
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for (i = 0; i < delay; i += 4)
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asm("nop");
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}
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static void program_cgu(const struct CGU_Settings *cgu)
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{
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const uintptr_t b = cgu->rbase;
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const bool use_extension0 = cgu->divex_S0SELEX >= 0;
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const bool use_extension1 = cgu->divex_S1SELEX >= 0;
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u32 temp;
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temp = OSEL(cgu->div_OSEL);
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temp |= SYSSEL(cgu->div_SYSSEL);
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temp |= CSEL(cgu->div_CSEL);
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temp |= DSEL(cgu->div_DSEL);
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temp |= (S0SEL(cgu->div_S0SEL));
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temp |= (S1SEL(cgu->div_S1SEL));
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temp &= ~BITM_CGU_DIV_LOCK;
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//Put PLL in to Bypass Mode
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writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPST,
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b + CGU_PLLCTL);
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while (!(readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP))
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;
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while (!((readl(b + CGU_STAT) & CGU_STAT_MASK) == CGU_STAT_ALGN_LOCK))
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;
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dmcdelay(1000);
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writel(temp & (~BITM_CGU_DIV_ALGN) & (~BITM_CGU_DIV_UPDT),
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b + CGU_DIV);
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dmcdelay(1000);
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temp = MSEL(cgu->ctl_MSEL) | DF(cgu->ctl_DF);
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if (use_extension0)
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temp |= BITM_CGU_CTL_S0SELEXEN;
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if (use_extension1)
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temp |= BITM_CGU_CTL_S1SELEXEN;
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writel(temp & (~BITM_CGU_CTL_LOCK), b + CGU_CTL);
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if (use_extension0 || use_extension1) {
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u32 mask = BITM_CGU_CTL_S1SELEXEN | BITM_CGU_CTL_S0SELEXEN;
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while (!(readl(b + CGU_CTL) & mask))
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;
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temp = readl(b + CGU_DIVEX);
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if (use_extension0) {
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temp &= ~BITM_CGU_DIVEX_S0SELEX;
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temp |= S0SELEX(cgu->divex_S0SELEX);
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}
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if (use_extension1) {
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temp &= ~BITM_CGU_DIVEX_S1SELEX;
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temp |= S1SELEX(cgu->divex_S1SELEX);
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}
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writel(temp, b + CGU_DIVEX);
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}
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dmcdelay(1000);
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//Take PLL out of Bypass Mode
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writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPCL,
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b + CGU_PLLCTL);
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while ((readl(b + CGU_STAT) &
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(BITM_CGU_STAT_PLLBP | BITM_CGU_STAT_CLKSALGN)))
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;
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dmcdelay(1000);
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if (cgu->clkoutsel >= 0) {
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temp = readl(b + CGU_CLKOUTSEL);
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temp &= ~BITM_CGU_CLKOUTSEL_CLKOUTSEL;
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temp |= CLKOUTSEL(cgu->clkoutsel);
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writel(temp, b + CGU_CLKOUTSEL);
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}
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}
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void adi_config_third_pll(void)
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{
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#if defined(CONFIG_CGU1_PLL3_VCO_MSEL) && defined(CONFIG_CGU1_PLL3_DCLK_DIV)
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u32 temp;
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u32 msel = CONFIG_CGU1_PLL3_VCO_MSEL - 1;
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u32 dsel = CONFIG_CGU1_PLL3_DCLK_DIV - 1;
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temp = readl(REG_MISC_REG10_tst_addr);
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temp &= 0xFFFE0000;
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writel(temp, REG_MISC_REG10_tst_addr);
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dmcdelay(4000u);
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//update MSEL [10:4]
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temp = readl(REG_MISC_REG10_tst_addr);
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temp |= ((msel << BITP_REG10_MSEL3) & BITM_REG10_MSEL3);
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writel(temp, REG_MISC_REG10_tst_addr);
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temp = readl(REG_MISC_REG10_tst_addr);
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temp |= 0x2;
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writel(temp, REG_MISC_REG10_tst_addr);
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dmcdelay(100000u);
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temp = readl(REG_MISC_REG10_tst_addr);
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temp |= 0x1;
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writel(temp, REG_MISC_REG10_tst_addr);
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temp = readl(REG_MISC_REG10_tst_addr);
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temp |= 0x800;
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writel(temp, REG_MISC_REG10_tst_addr);
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temp = readl(REG_MISC_REG10_tst_addr);
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temp &= 0xFFFFF7F8;
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writel(temp, REG_MISC_REG10_tst_addr);
|
|
|
|
dmcdelay(4000u);
|
|
|
|
temp = readl(REG_MISC_REG10_tst_addr);
|
|
temp |= ((dsel << BITP_REG10_DSEL3) & BITM_REG10_DSEL3);
|
|
writel(temp, REG_MISC_REG10_tst_addr);
|
|
|
|
temp = readl(REG_MISC_REG10_tst_addr);
|
|
temp |= 0x4;
|
|
writel(temp, REG_MISC_REG10_tst_addr);
|
|
|
|
dmcdelay(100000u);
|
|
|
|
temp = readl(REG_MISC_REG10_tst_addr);
|
|
temp |= 0x1;
|
|
writel(temp, REG_MISC_REG10_tst_addr);
|
|
|
|
temp = readl(REG_MISC_REG10_tst_addr);
|
|
temp |= 0x800;
|
|
writel(temp, REG_MISC_REG10_tst_addr);
|
|
#endif
|
|
}
|
|
|
|
static void Active_To_Fullon(const struct CGU_Settings *pCGU)
|
|
{
|
|
u32 tmp;
|
|
|
|
while (1) {
|
|
tmp = readl(pCGU->rbase + CGU_STAT);
|
|
if ((tmp & BITM_CGU_STAT_PLLEN) &&
|
|
(tmp & BITM_CGU_STAT_PLLBP))
|
|
break;
|
|
}
|
|
|
|
writel(BITM_CGU_PLLCTL_PLLBPCL, pCGU->rbase + CGU_PLLCTL);
|
|
|
|
while (1) {
|
|
tmp = readl(pCGU->rbase + CGU_STAT);
|
|
if ((tmp & BITM_CGU_STAT_PLLEN) &&
|
|
~(tmp & BITM_CGU_STAT_PLLBP) &&
|
|
~(tmp & BITM_CGU_STAT_CLKSALGN))
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void CGU_Init(const struct CGU_Settings *pCGU)
|
|
{
|
|
const uintptr_t b = pCGU->rbase;
|
|
|
|
#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
|
|
if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLEN)
|
|
writel(BITM_CGU_PLLCTL_PLLEN, b + CGU_PLLCTL);
|
|
|
|
dmcdelay(1000);
|
|
#endif
|
|
|
|
/* Check if processor is in Active mode */
|
|
if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP)
|
|
Active_To_Fullon(pCGU);
|
|
|
|
#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64)
|
|
dmcdelay(1000);
|
|
#endif
|
|
|
|
program_cgu(pCGU);
|
|
}
|
|
|
|
void cgu_init(void)
|
|
{
|
|
const struct CGU_Settings dividers0 = {
|
|
.rbase = CGU0_REGBASE,
|
|
.ctl_MSEL = CONFIG_CGU0_VCO_MULT,
|
|
.ctl_DF = CONFIG_CGU0_DF_DIV,
|
|
.div_CSEL = CONFIG_CGU0_CCLK_DIV,
|
|
.div_SYSSEL = CONFIG_CGU0_SCLK_DIV,
|
|
.div_S0SEL = VAL_CGU0_SCLK0_DIV,
|
|
.div_S1SEL = VAL_CGU0_SCLK1_DIV,
|
|
.div_DSEL = CONFIG_CGU0_DCLK_DIV,
|
|
.div_OSEL = CONFIG_CGU0_OCLK_DIV,
|
|
.divex_S0SELEX = VAL_CGU0_DIV_S0SELEX,
|
|
.divex_S1SELEX = VAL_CGU0_DIV_S1SELEX,
|
|
.clkoutsel = VAL_CGU0_CLKOUTSEL,
|
|
};
|
|
const struct CGU_Settings dividers1 = {
|
|
.rbase = CGU1_REGBASE,
|
|
.ctl_MSEL = CONFIG_CGU1_VCO_MULT,
|
|
.ctl_DF = CONFIG_CGU1_DF_DIV,
|
|
.div_CSEL = CONFIG_CGU1_CCLK_DIV,
|
|
.div_SYSSEL = CONFIG_CGU1_SCLK_DIV,
|
|
.div_S0SEL = VAL_CGU1_SCLK0_DIV,
|
|
.div_S1SEL = VAL_CGU1_SCLK1_DIV,
|
|
.div_DSEL = CONFIG_CGU1_DCLK_DIV,
|
|
.div_OSEL = CONFIG_CGU1_OCLK_DIV,
|
|
.divex_S0SELEX = VAL_CGU1_DIV_S0SELEX,
|
|
.divex_S1SELEX = VAL_CGU1_DIV_S1SELEX,
|
|
.clkoutsel = VAL_CGU1_CLKOUTSEL,
|
|
};
|
|
|
|
CGU_Init(÷rs0);
|
|
CGU_Init(÷rs1);
|
|
}
|
|
|
|
#define CONFIGURE_CDU0(a, b, c) \
|
|
writel(a, b); \
|
|
while (readl(REG_CDU0_STAT) & (1 << (c)))
|
|
|
|
void cdu_init(void)
|
|
{
|
|
while (readl(REG_CDU0_STAT) & 0xffff)
|
|
;
|
|
writel((CONFIG_CDU0_CGU1_CLKIN & 0x1), REG_CDU0_CLKINSEL);
|
|
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO0, REG_CDU0_CFG0, 0);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO1, REG_CDU0_CFG1, 1);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO2, REG_CDU0_CFG2, 2);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO3, REG_CDU0_CFG3, 3);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO4, REG_CDU0_CFG4, 4);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO5, REG_CDU0_CFG5, 5);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO6, REG_CDU0_CFG6, 6);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO7, REG_CDU0_CFG7, 7);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO8, REG_CDU0_CFG8, 8);
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO9, REG_CDU0_CFG9, 9);
|
|
#ifdef CONFIG_CDU0_CLKO10
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO10, REG_CDU0_CFG10, 10);
|
|
#endif
|
|
#ifdef CONFIG_CDU0_CLKO12
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO12, REG_CDU0_CFG12, 12);
|
|
#endif
|
|
#ifdef CONFIG_CDU0_CLKO13
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO13, REG_CDU0_CFG13, 13);
|
|
#endif
|
|
#ifdef CONFIG_CDU0_CLKO14
|
|
CONFIGURE_CDU0(CONFIG_CDU0_CLKO14, REG_CDU0_CFG14, 14);
|
|
#endif
|
|
}
|
|
|
|
void clks_init(void)
|
|
{
|
|
adi_dmc_reset_lanes(true);
|
|
|
|
cdu_init();
|
|
cgu_init();
|
|
|
|
adi_config_third_pll();
|
|
|
|
adi_dmc_reset_lanes(false);
|
|
}
|