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dedea0d18d
Patch introduces: * chip_id API - useful for various things, but used now for device_id (did) generation as mentioned in [1] on our private board code. Our device_id is calculated by means of permutations of chip_id value. * new SoCs (a1, s4, etc) are usually coming with the support of chip_id v2 right away, whereas secure monitors on old SoCs (like axg, g12b, g12a, etc) may support only chip_id v1. Chip_id API handles both cases * meson_sm_get_serial() is described via chip_id API. Links: [1] https://lore.kernel.org/linux-arm-kernel/202311242104.RjBPI3uI-lkp@intel.com/T/#m630fbeea6a6e7d531290b5c0af205af4fb979757 Signed-off-by: Viacheslav Bocharov <adeep@lexina.in> Co-developed-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com> Link: https://lore.kernel.org/r/20250210-meson_chip_id_all_vers-v1-3-b98f8b6880b8@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
138 lines
3.6 KiB
C
138 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*/
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#ifndef __MESON_SM_H__
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#define __MESON_SM_H__
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#include <asm/types.h>
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/**
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* meson_sm_read_efuse - read efuse memory into buffer
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*
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* @offset: offset from the start efuse memory
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* @buffer: pointer to buffer
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* @size: number of bytes to read
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* @return: number of bytes read
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*/
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ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
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/**
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* meson_sm_write_efuse - write into efuse memory from buffer
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*
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* @offset: offset from the start efuse memory
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* @buffer: pointer to buffer
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* @size: number of bytes to write
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* @return: number of bytes written
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*/
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ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
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#define SM_SERIAL_SIZE 12
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#define MESON_CPU_ID_SZ 4
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#define MESON_CHIP_ID_SZ 16
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/**
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* union meson_cpu_id - Amlogic cpu_id.
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* @raw: buffer to hold the cpu_id value as sequential bytes.
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* @val: cpu_id represented as 32 bit value.
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*/
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union meson_cpu_id {
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u8 raw[MESON_CPU_ID_SZ];
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u32 val;
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};
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/**
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* struct meson_sm_chip_id - Amlogic chip_id.
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* @cpu_id: cpu_id value, which is distinct from socinfo in that the order of
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* PACK & MINOR bytes are swapped according to Amlogic chip_id format.
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* @serial: 12 byte unique SoC number, identifying particular die, read
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* usually from efuse OTP storage. Serial comes in little-endian
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* order.
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*/
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struct meson_sm_chip_id {
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union meson_cpu_id cpu_id;
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u8 serial[SM_SERIAL_SIZE];
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};
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/**
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* meson_sm_get_serial - read chip unique serial (OTP data) into buffer
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*
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* @buffer: pointer to buffer
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* @size: buffer size.
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*
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* Serial is returned in big-endian order.
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*
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* @return: zero on success or -errno on failure
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*/
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int meson_sm_get_serial(void *buffer, size_t size);
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/**
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* meson_sm_get_chip_id - read Amlogic chip_id
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*
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* @chip_id: pointer to buffer capable to hold the struct meson_sm_chip_id
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*
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* Amlogic SoCs support 2 versions of chip_id. Function requests the newest
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* one (v2), but if chip_id v2 is not supported, then secure monitor returns
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* v1. All differences between v1 and v2 versions are handled by this function
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* and chip_id is returned in unified format.
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*
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* chip_id contains serial, which is returned here in little-endian order.
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*
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* @return: 0 on success or -errno on failure
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*/
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int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id);
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enum {
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REBOOT_REASON_COLD = 0,
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REBOOT_REASON_NORMAL = 1,
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REBOOT_REASON_RECOVERY = 2,
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REBOOT_REASON_UPDATE = 3,
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REBOOT_REASON_FASTBOOT = 4,
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REBOOT_REASON_SUSPEND_OFF = 5,
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REBOOT_REASON_HIBERNATE = 6,
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REBOOT_REASON_BOOTLOADER = 7,
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REBOOT_REASON_SHUTDOWN_REBOOT = 8,
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REBOOT_REASON_RPMBP = 9,
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REBOOT_REASON_CRASH_DUMP = 11,
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REBOOT_REASON_KERNEL_PANIC = 12,
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REBOOT_REASON_WATCHDOG_REBOOT = 13,
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};
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/**
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* meson_sm_get_reboot_reason - get reboot reason
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*/
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int meson_sm_get_reboot_reason(void);
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#define PWRDM_OFF 0
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#define PWRDM_ON 1
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/**
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* meson_sm_pwrdm_set - do command at specified power domain.
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*
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* @index: power domain index.
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* @cmd: command index.
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* @return: zero on success or error code on failure.
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*/
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int meson_sm_pwrdm_set(size_t index, int cmd);
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/**
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* meson_sm_pwrdm_off - disable specified power domain.
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*
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* @index: power domain index.
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* @return: zero on success or error code on failure.
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*/
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#define meson_sm_pwrdm_off(index) \
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meson_sm_pwrdm_set(index, PWRDM_OFF)
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/**
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* meson_sm_pwrdm_on - enable specified power domain.
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*
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* @index: power domain index.
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* @return: zero on success or error code on failure.
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*/
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#define meson_sm_pwrdm_on(index) \
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meson_sm_pwrdm_set(index, PWRDM_ON)
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#endif /* __MESON_SM_H__ */
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