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f63a30f1c0
The STM32 System Bus is an internal bus on which devices are connected. ETZPC is a peripheral overseeing the firewall bus that configures and control access to the peripherals connected on it. For more information on which peripheral is securable, please read the STM32MP13 or STM32MP15 reference manual. Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
256 lines
3.1 KiB
Plaintext
256 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2018
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*/
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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gpio25 = &gpioz;
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pinctrl0 = &pinctrl;
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pinctrl1 = &pinctrl_z;
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};
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binman: binman {
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multiple-images;
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};
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clocks {
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bootph-all;
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};
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/* need PSCI for sysreset during board_f */
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psci {
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bootph-some-ram;
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};
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reboot {
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bootph-all;
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compatible = "syscon-reboot";
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regmap = <&rcc>;
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offset = <0x404>;
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mask = <0x1>;
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};
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soc {
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bootph-all;
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ddr: ddr@5a003000 {
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bootph-all;
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compatible = "st,stm32mp1-ddr";
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reg = <0x5a003000 0x550
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0x5a004000 0x234>;
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status = "okay";
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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bootph-pre-ram;
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opp-650000000 {
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bootph-pre-ram;
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opp-hz = /bits/ 64 <650000000>;
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opp-microvolt = <1200000>;
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opp-supported-hw = <0x1>;
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};
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opp-800000000 {
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bootph-pre-ram;
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1350000>;
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opp-supported-hw = <0x2>;
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};
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};
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};
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&bsec {
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bootph-all;
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};
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&clk_csi {
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bootph-all;
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};
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&clk_hsi {
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bootph-all;
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};
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&clk_hse {
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bootph-all;
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};
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&clk_lsi {
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bootph-all;
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};
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&clk_lse {
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bootph-all;
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};
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&cpu0 {
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nvmem-cells = <&part_number_otp>;
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nvmem-cell-names = "part_number";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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&etzpc {
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bootph-all;
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};
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&gpioa {
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bootph-all;
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};
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&gpiob {
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bootph-all;
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};
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&gpioc {
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bootph-all;
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};
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&gpiod {
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bootph-all;
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};
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&gpioe {
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bootph-all;
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};
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&gpiof {
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bootph-all;
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};
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&gpiog {
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bootph-all;
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};
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&gpioh {
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bootph-all;
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};
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&gpioi {
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bootph-all;
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};
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&gpioj {
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bootph-all;
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};
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&gpiok {
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bootph-all;
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};
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&gpioz {
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bootph-all;
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};
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&iwdg2 {
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bootph-all;
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};
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/* pre-reloc probe = reserve video frame buffer in video_reserve() */
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<dc {
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bootph-some-ram;
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};
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/* temp = waiting kernel update */
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&m4_rproc {
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resets = <&rcc MCU_R>,
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<&rcc MCU_HOLD_BOOT_R>;
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reset-names = "mcu_rst", "hold_boot";
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};
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&pinctrl {
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bootph-all;
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};
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&pinctrl_z {
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bootph-all;
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};
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&pwr_regulators {
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bootph-all;
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};
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&rcc {
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bootph-all;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
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<&clk_lse>, <&clk_lsi>;
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};
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&usart1 {
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resets = <&rcc USART1_R>;
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};
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&usart2 {
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resets = <&rcc USART2_R>;
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};
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&usart3 {
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resets = <&rcc USART3_R>;
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};
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&uart4 {
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resets = <&rcc UART4_R>;
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};
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&uart5 {
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resets = <&rcc UART5_R>;
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};
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&usart6 {
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resets = <&rcc USART6_R>;
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};
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&uart7 {
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resets = <&rcc UART7_R>;
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};
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&uart8{
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resets = <&rcc UART8_R>;
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};
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#if defined(CONFIG_STM32MP15X_STM32IMAGE)
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&binman {
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u-boot-stm32 {
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filename = "u-boot.stm32";
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mkimage {
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args = "-T stm32image -a 0xc0100000 -e 0xc0100000";
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u-boot {
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};
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};
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};
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};
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#endif
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#if defined(CONFIG_SPL)
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&binman {
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spl-stm32 {
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filename = "u-boot-spl.stm32";
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mkimage {
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args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500";
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u-boot-spl {
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no-write-symbols;
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};
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};
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};
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};
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#endif
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