mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-14 19:26:58 +02:00
52891fda68
Cache allocation for dirty writes in the CCU system cache was disabled for performance optimization. Signed-off-by: Tingting Meng <tingting.meng@altera.com>
746 lines
19 KiB
Plaintext
746 lines
19 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2024 Intel Corporation <www.intel.com>
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*/
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#include "socfpga_soc64_fit-u-boot.dtsi"
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/{
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memory {
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#address-cells = <2>;
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#size-cells = <2>;
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bootph-all;
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};
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soc {
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bootph-all;
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socfpga_ccu_config: socfpga-ccu-config {
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compatible = "intel,socfpga-dtreg";
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#address-cells = <1>;
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#size-cells = <1>;
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bootph-all;
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/* DSU */
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i_ccu_caiu0@1c000000 {
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reg = <0x1c000000 0x00001000>;
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intel,offset-settings =
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/* CAIUMIFSR */
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<0x000003c4 0x00000000 0x07070777>,
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/* DII1_MPFEREGS */
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<0x00000414 0x00018000 0xffffffff>,
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<0x00000418 0x00000000 0x000000ff>,
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<0x00000410 0xc0e00200 0xc1f03e1f>,
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/* DII2_GICREGS */
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<0x00000424 0x0001d000 0xffffffff>,
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<0x00000428 0x00000000 0x000000ff>,
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<0x00000420 0xc0800400 0xc1f03e1f>,
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/* NCAIU0_LWSOC2FPGA */
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<0x00000444 0x00020000 0xffffffff>,
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<0x00000448 0x00000000 0x000000ff>,
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<0x00000440 0xc1100006 0xc1f03e1f>,
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/* NCAIU0_SOC2FPGA_1G */
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<0x00000454 0x00040000 0xffffffff>,
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<0x00000458 0x00000000 0x000000ff>,
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<0x00000450 0xc1200006 0xc1f03e1f>,
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/* DMI_SDRAM_2G */
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<0x00000464 0x00080000 0xffffffff>,
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<0x00000468 0x00000000 0x000000ff>,
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/* NCAIU0_SOC2FPGA_16G */
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<0x00000474 0x00400000 0xffffffff>,
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<0x00000478 0x00000000 0x000000ff>,
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<0x00000470 0xc1600006 0xc1f03e1f>,
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/* DMI_SDRAM_30G */
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<0x00000484 0x00800000 0xffffffff>,
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<0x00000488 0x00000000 0x000000ff>,
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/* NCAIU0_SOC2FPGA_256G */
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<0x00000494 0x04000000 0xffffffff>,
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<0x00000498 0x00000000 0x000000ff>,
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<0x00000490 0xc1a00006 0xc1f03e1f>,
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/* DMI_SDRAM_480G */
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<0x000004a4 0x08000000 0xffffffff>,
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<0x000004a8 0x00000000 0x000000ff>;
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bootph-all;
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};
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/* FPGA2SOC */
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i_ccu_ncaiu0@1c001000 {
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reg = <0x1c001000 0x00001000>;
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intel,offset-settings =
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/* NCAIU0MIFSR */
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<0x000003c4 0x00000000 0x07070777>,
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/* PSS */
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<0x00000404 0x00010000 0xffffffff>,
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<0x00000408 0x00000000 0x000000ff>,
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<0x00000400 0xC0F00000 0xc1f03e1f>,
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/* DII1_MPFEREGS */
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<0x00000414 0x00018000 0xffffffff>,
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<0x00000418 0x00000000 0x000000ff>,
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<0x00000410 0xc0e00200 0xc1f03e1f>,
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/* NCAIU0_LWSOC2FPGA */
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<0x00000444 0x00020000 0xffffffff>,
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<0x00000448 0x00000000 0x000000ff>,
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<0x00000440 0xc1100006 0xc1f03e1f>,
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/* NCAIU0_SOC2FPGA_1G */
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<0x00000454 0x00040000 0xffffffff>,
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<0x00000458 0x00000000 0x000000ff>,
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<0x00000450 0xc1200006 0xc1f03e1f>,
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/* DMI_SDRAM_2G */
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<0x00000464 0x00080000 0xffffffff>,
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<0x00000468 0x00000000 0x000000ff>,
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/* NCAIU0_SOC2FPGA_16G */
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<0x00000474 0x00400000 0xffffffff>,
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<0x00000478 0x00000000 0x000000ff>,
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<0x00000470 0xc1600006 0xc1f03e1f>,
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/* DMI_SDRAM_30G */
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<0x00000484 0x00800000 0xffffffff>,
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<0x00000488 0x00000000 0x000000ff>,
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/* NCAIU0_SOC2FPGA_256G */
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<0x00000494 0x04000000 0xffffffff>,
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<0x00000498 0x00000000 0x000000ff>,
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<0x00000490 0xc1a00006 0xc1f03e1f>,
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/* DMI_SDRAM_480G */
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<0x000004a4 0x08000000 0xffffffff>,
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<0x000004a8 0x00000000 0x000000ff>;
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bootph-all;
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};
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/* GIC_M */
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i_ccu_ncaiu1@1c002000 {
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reg = <0x1c002000 0x00001000>;
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intel,offset-settings =
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/* NCAIU1MIFSR */
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<0x000003c4 0x00000000 0x07070777>,
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/* DMI_SDRAM_2G */
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<0x00000464 0x00080000 0xffffffff>,
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<0x00000468 0x00000000 0x000000ff>,
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/* DMI_SDRAM_30G */
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<0x00000484 0x00800000 0xffffffff>,
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<0x00000488 0x00000000 0x000000ff>,
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/* DMI_SDRAM_480G */
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<0x000004a4 0x08000000 0xffffffff>,
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<0x000004a8 0x00000000 0x000000ff>;
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bootph-all;
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};
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/* SMMU */
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i_ccu_ncaiu2@1c003000 {
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reg = <0x1c003000 0x00001000>;
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intel,offset-settings =
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/* NCAIU2MIFSR */
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<0x000003c4 0x00000000 0x07070777>,
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/* DMI_SDRAM_2G */
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<0x00000464 0x00080000 0xffffffff>,
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<0x00000468 0x00000000 0x000000ff>,
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/* DMI_SDRAM_30G */
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<0x00000484 0x00800000 0xffffffff>,
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<0x00000488 0x00000000 0x000000ff>,
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/* DMI_SDRAM_480G */
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<0x000004a4 0x08000000 0xffffffff>,
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<0x000004a8 0x00000000 0x000000ff>;
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bootph-all;
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};
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/* PSS NOC */
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i_ccu_ncaiu3@1c004000 {
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reg = <0x1c004000 0x00001000>;
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intel,offset-settings =
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/* NCAIU3MIFSR */
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<0x000003c4 0x00000000 0x07070777>,
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/* DII1_MPFEREGS */
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<0x00000414 0x00018000 0xffffffff>,
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<0x00000418 0x00000000 0x000000ff>,
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<0x00000410 0xc0e00200 0xc1f03e1f>,
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/* DMI_SDRAM_2G */
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<0x00000464 0x00080000 0xffffffff>,
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<0x00000468 0x00000000 0x000000ff>,
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/* DMI_SDRAM_30G */
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<0x00000484 0x00800000 0xffffffff>,
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<0x00000488 0x00000000 0x000000ff>,
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/* DMI_SDRAM_480G */
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<0x000004a4 0x08000000 0xffffffff>,
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<0x000004a8 0x00000000 0x000000ff>;
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bootph-all;
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};
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/* DCE0 */
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i_ccu_dce0@1c005000 {
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reg = <0x1c005000 0x00001000>;
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intel,offset-settings =
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/* DCEUMIFSR0 */
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<0x000003c4 0x00000000 0x07070777>,
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/* DMI_SDRAM_2G */
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<0x00000464 0x00080000 0xffffffff>,
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<0x00000468 0x00000000 0x000000ff>,
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/* DMI_SDRAM_30G */
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<0x00000484 0x00800000 0xffffffff>,
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<0x00000488 0x00000000 0x000000ff>,
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/* DMI_SDRAM_480G */
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<0x000004a4 0x08000000 0xffffffff>,
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<0x000004a8 0x00000000 0x000000ff>;
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bootph-all;
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};
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/* DCE1 */
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i_ccu_dce1@1c006000 {
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reg = <0x1c006000 0x00001000>;
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intel,offset-settings =
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/* DCEUMIFSR1 */
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<0x000003c4 0x00000000 0x07070777>,
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/* DMI_SDRAM_2G */
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<0x00000464 0x00080000 0xffffffff>,
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<0x00000468 0x00000000 0x000000ff>,
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/* DMI_SDRAM_30G */
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<0x00000484 0x00800000 0xffffffff>,
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<0x00000488 0x00000000 0x000000ff>,
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/* DMI_SDRAM_480G */
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<0x000004a4 0x08000000 0xffffffff>,
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<0x000004a8 0x00000000 0x000000ff>;
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bootph-all;
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};
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/* DMI0 */
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i_ccu_dmi0@1c007000 {
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reg = <0x1c007000 0x00001000>;
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intel,offset-settings =
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/* DMIUSMCTCR */
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<0x00000300 0x00000001 0x00000003>,
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<0x00000300 0x00000003 0x00000003>,
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<0x00000308 0x00000004 0x0000001F>;
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bootph-all;
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};
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/* DMI1 */
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i_ccu_dmi0@1c008000 {
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reg = <0x1c008000 0x00001000>;
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intel,offset-settings =
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/* DMIUSMCTCR */
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<0x00000300 0x00000001 0x00000003>,
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<0x00000300 0x00000003 0x00000003>,
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<0x00000308 0x00000004 0x0000001F>;
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bootph-all;
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};
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};
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socfpga_firewall_config: socfpga-firewall-config {
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compatible = "intel,socfpga-dtreg";
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#address-cells = <1>;
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#size-cells = <1>;
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bootph-all;
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/* L4 peripherals firewall */
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noc_fw_l4_per@10d21000 {
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reg = <0x10d21000 0x0000008c>;
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intel,offset-settings =
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/* NAND */
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<0x00000000 0x01010001 0x01010001>,
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/* USB0 */
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<0x0000000c 0x01010001 0x01010001>,
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/* USB1 */
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<0x00000010 0x01010001 0x01010001>,
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/* SPI_MAIN0 */
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<0x0000001c 0x01010301 0x01010301>,
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/* SPI_MAIN1 */
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<0x00000020 0x01010301 0x01010301>,
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/* SPI_SECONDARY0 */
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<0x00000024 0x01010301 0x01010301>,
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/* SPI_SECONDARY1 */
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<0x00000028 0x01010301 0x01010301>,
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/* EMAC0 */
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<0x0000002c 0x01010001 0x01010001>,
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/* EMAC1 */
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<0x00000030 0x01010001 0x01010001>,
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/* EMAC2 */
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<0x00000034 0x01010001 0x01010001>,
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/* SDMMC */
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<0x00000040 0x01010001 0x01010001>,
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/* GPIO0 */
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<0x00000044 0x01010301 0x01010301>,
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/* GPIO1 */
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<0x00000048 0x01010301 0x01010301>,
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/* I2C0 */
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<0x00000050 0x01010301 0x01010301>,
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/* I2C1 */
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<0x00000054 0x01010301 0x01010301>,
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/* I2C2 */
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<0x00000058 0x01010301 0x01010301>,
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/* I2C3 */
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<0x0000005c 0x01010301 0x01010301>,
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/* I2C4 */
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<0x00000060 0x01010301 0x01010301>,
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/* SP_TIMER0 */
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<0x00000064 0x01010301 0x01010301>,
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/* SP_TIMER1 */
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<0x00000068 0x01010301 0x01010301>,
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/* UART0 */
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<0x0000006c 0x01010301 0x01010301>,
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/* UART1 */
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<0x00000070 0x01010301 0x01010301>,
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/* I3C0 */
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<0x00000074 0x01010301 0x01010301>,
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/* I3C1 */
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<0x00000078 0x01010301 0x01010301>,
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/* DMA0 */
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<0x0000007c 0x01010001 0x01010001>,
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/* DMA1 */
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<0x00000080 0x01010001 0x01010001>,
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/* COMBO_PHY */
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<0x00000084 0x01010001 0x01010001>,
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/* NAND_SDMA */
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<0x00000088 0x01010301 0x01010301>;
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bootph-all;
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};
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/* L4 system firewall */
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noc_fw_l4_sys@10d21100 {
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reg = <0x10d21100 0x00000098>;
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intel,offset-settings =
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/* DMA_ECC */
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<0x00000008 0x01010001 0x01010001>,
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/* EMAC0RX_ECC */
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<0x0000000c 0x01010001 0x01010001>,
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/* EMAC0TX_ECC */
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<0x00000010 0x01010001 0x01010001>,
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/* EMAC1RX_ECC */
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<0x00000014 0x01010001 0x01010001>,
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/* EMAC1TX_ECC */
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<0x00000018 0x01010001 0x01010001>,
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/* EMAC2RX_ECC */
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<0x0000001c 0x01010001 0x01010001>,
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/* EMAC2TX_ECC */
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<0x00000020 0x01010001 0x01010001>,
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/* NAND_ECC */
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<0x0000002c 0x01010001 0x01010001>,
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/* NAND_READ_ECC */
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<0x00000030 0x01010001 0x01010001>,
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/* NAND_WRITE_ECC */
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<0x00000034 0x01010001 0x01010001>,
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/* OCRAM_ECC */
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<0x00000038 0x01010001 0x01010001>,
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/* SDMMC_ECC */
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<0x00000040 0x01010001 0x01010001>,
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/* USB0_ECC */
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<0x00000044 0x01010001 0x01010001>,
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/* USB1_CACHEECC */
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<0x00000048 0x01010001 0x01010001>,
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/* CLOCK_MANAGER */
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<0x0000004c 0x01010001 0x01010001>,
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/* IO_MANAGER */
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<0x00000054 0x01010001 0x01010001>,
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/* RESET_MANAGER */
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<0x00000058 0x01010001 0x01010001>,
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/* SYSTEM_MANAGER */
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<0x0000005c 0x01010001 0x01010001>,
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/* OSC0_TIMER */
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<0x00000060 0x01010301 0x01010301>,
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/* OSC1_TIMER0*/
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<0x00000064 0x01010301 0x01010301>,
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/* WATCHDOG0 */
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<0x00000068 0x01010301 0x01010301>,
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/* WATCHDOG1 */
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<0x0000006c 0x01010301 0x01010301>,
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/* WATCHDOG2 */
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<0x00000070 0x01010301 0x01010301>,
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/* WATCHDOG3 */
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<0x00000074 0x01010301 0x01010301>,
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/* DAP */
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<0x00000078 0x03010001 0x03010001>,
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/* WATCHDOG4 */
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<0x0000007c 0x01010301 0x01010301>,
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/* POWER_MANAGER */
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<0x00000080 0x01010001 0x01010001>,
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/* USB1_RXECC */
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<0x00000084 0x01010001 0x01010001>,
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/* USB1_TXECC */
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<0x00000088 0x01010001 0x01010001>,
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/* L4_NOC_PROBES */
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<0x00000090 0x01010001 0x01010001>,
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/* L4_NOC_QOS */
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<0x00000094 0x01010001 0x01010001>;
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bootph-all;
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};
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/* Light weight SoC2FPGA */
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noc_fw_lwsoc2fpga@10d21300 {
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reg = <0x10d21300 0x0000004>;
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intel,offset-settings =
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/* LWSOC2FPGA_CSR */
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<0x00000000 0x0ffe0301 0x0ffe0301>;
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bootph-all;
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};
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/* SoC2FPGA */
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noc_fw_soc2fpga@10d21200 {
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reg = <0x10d21200 0x0000004>;
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intel,offset-settings =
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/* SOC2FPGA_CSR */
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<0x00000000 0x0ffe0301 0x0ffe0301>;
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bootph-all;
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};
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/* TCU */
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noc_fw_tcu@10d21400 {
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reg = <0x10d21400 0x0000004>;
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intel,offset-settings =
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/* TCU_CSR */
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<0x00000000 0x01010001 0x01010001>;
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bootph-all;
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};
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};
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socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
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compatible = "intel,socfpga-dtreg";
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#address-cells = <1>;
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#size-cells = <1>;
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bootph-all;
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/* DSU */
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i_ccu_caiu0@1c000000 {
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reg = <0x1c000000 0x00001000>;
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intel,offset-settings =
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/* CAIUAMIGR */
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<0x000003c0 0x00000003 0x0000001f>,
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/* DMI_SDRAM_2G */
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<0x00000460 0x81300006 0xc1f03e1f>,
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/* DMI_SDRAM_30G */
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<0x00000480 0x81700006 0xc1f03e1f>,
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/* DMI_SDRAM_480G */
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<0x000004a0 0x81b00006 0xc1f03e1f>;
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bootph-all;
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};
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/* FPGA2SOC */
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i_ccu_ncaiu0@1c001000 {
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reg = <0x1c001000 0x00001000>;
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intel,offset-settings =
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/* NCAIU0AMIGR */
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<0x000003c0 0x00000003 0x0000001f>,
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/* DMI_SDRAM_2G */
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<0x00000460 0x81300006 0xc1f03e1f>,
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/* DMI_SDRAM_30G */
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<0x00000480 0x81700006 0xc1f03e1f>,
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/* DMI_SDRAM_480G */
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<0x000004a0 0x81b00006 0xc1f03e1f>;
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bootph-all;
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};
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/* GIC_M */
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i_ccu_ncaiu1@1c002000 {
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reg = <0x1c002000 0x00001000>;
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intel,offset-settings =
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/* NCAIU1AMIGR */
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<0x000003c0 0x00000003 0x0000001f>,
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/* DMI_SDRAM_2G */
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<0x00000460 0x81300006 0xc1f03e1f>,
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/* DMI_SDRAM_30G */
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<0x00000480 0x81700006 0xc1f03e1f>,
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/* DMI_SDRAM_480G */
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<0x000004a0 0x81b00006 0xc1f03e1f>;
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bootph-all;
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};
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/* SMMU */
|
|
i_ccu_ncaiu2@1c003000 {
|
|
reg = <0x1c003000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* NCAIU2AMIGR */
|
|
<0x000003c0 0x00000003 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81300006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81700006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81b00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* PSS NOC */
|
|
i_ccu_ncaiu3@1c004000 {
|
|
reg = <0x1c004000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* NCAIU3AMIGR */
|
|
<0x000003c0 0x00000003 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81300006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81700006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81b00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* DCE0 */
|
|
i_ccu_dce0@1c005000 {
|
|
reg = <0x1c005000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* DCEUAMIGR0 */
|
|
<0x000003c0 0x00000003 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81300006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81700006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81b00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* DCE1 */
|
|
i_ccu_dce1@1c006000 {
|
|
reg = <0x1c006000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* DCEUAMIGR1 */
|
|
<0x000003c0 0x00000003 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81300006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81700006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81b00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
|
|
compatible = "intel,socfpga-dtreg";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
bootph-all;
|
|
|
|
/* DSU */
|
|
i_ccu_caiu0@1c000000 {
|
|
reg = <0x1c000000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* CAIUAMIGR */
|
|
<0x000003c0 0x00000001 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81200006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81600006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81a00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* FPGA2SOC */
|
|
i_ccu_ncaiu0@1c001000 {
|
|
reg = <0x1c001000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* NCAIU0AMIGR */
|
|
<0x000003c0 0x00000001 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81200006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81600006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81a00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* GIC_M */
|
|
i_ccu_ncaiu1@1c002000 {
|
|
reg = <0x1c002000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* NCAIU1AMIGR */
|
|
<0x000003c0 0x00000001 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81200006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81600006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81a00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* SMMU */
|
|
i_ccu_ncaiu2@1c003000 {
|
|
reg = <0x1c003000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* NCAIU2AMIGR */
|
|
<0x000003c0 0x00000001 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81200006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81600006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81a00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* PSS NOC */
|
|
i_ccu_ncaiu3@1c004000 {
|
|
reg = <0x1c004000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* NCAIU3AMIGR */
|
|
<0x000003c0 0x00000001 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81200006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81600006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81a00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* DCE0 */
|
|
i_ccu_dce0@1c005000 {
|
|
reg = <0x1c005000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* DCEUAMIGR0 */
|
|
<0x000003c0 0x00000001 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81200006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81600006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81a00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
|
|
/* DCE1 */
|
|
i_ccu_dce1@1c006000 {
|
|
reg = <0x1c006000 0x00001000>;
|
|
intel,offset-settings =
|
|
/* DCEUAMIGR1 */
|
|
<0x000003c0 0x00000001 0x0000001f>,
|
|
/* DMI_SDRAM_2G */
|
|
<0x00000460 0x81200006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_30G */
|
|
<0x00000480 0x81600006 0xc1f03e1f>,
|
|
/* DMI_SDRAM_480G */
|
|
<0x000004a0 0x81a00006 0xc1f03e1f>;
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
socfpga_smmu_secure_config: socfpga-smmu-secure-config {
|
|
compatible = "intel,socfpga-dtreg";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
bootph-all;
|
|
|
|
/* System manager */
|
|
i_sys_mgt_sysmgr_csr@10d12000 {
|
|
reg = <0x10d12000 0x00000500>;
|
|
intel,offset-settings =
|
|
/* dma_tbu_stream_ctrl_reg_0_dma0 */
|
|
<0x0000017c 0x00000000 0x0000003f>,
|
|
/* dma_tbu_stream_ctrl_reg_0_dma1 */
|
|
<0x00000180 0x00000000 0x0000003f>,
|
|
/* sdm_tbu_stream_ctrl_reg_1_sdm */
|
|
<0x00000184 0x00000000 0x0000003f>,
|
|
/* io_tbu_stream_ctrl_reg_2_usb2 */
|
|
<0x00000188 0x00000000 0x0000003f>,
|
|
/* io_tbu_stream_ctrl_reg_2_sdmmc */
|
|
<0x00000190 0x00000000 0x0000003f>,
|
|
/* io_tbu_stream_ctrl_reg_2_nand */
|
|
<0x00000194 0x00000000 0x0000003f>,
|
|
/* io_tbu_stream_ctrl_reg_2_etr */
|
|
<0x00000198 0x00000000 0x0000003f>,
|
|
/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
|
|
<0x0000019c 0x00000000 0x0000003f>,
|
|
/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
|
|
<0x000001a0 0x00000000 0x0000003f>,
|
|
/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
|
|
<0x000001a4 0x00000000 0x0000003f>;
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
|
|
compatible = "intel,socfpga-dtreg";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
bootph-all;
|
|
|
|
/* noc fw mpfe csr */
|
|
i_noc_fw_mpfe_csr@18000d00 {
|
|
reg = <0x18000d00 0x00000100>;
|
|
intel,offset-settings =
|
|
/* mpfe scr io96b0 reg*/
|
|
<0x00000000 0x00000001 0x00010101>,
|
|
/* mpfe scr io96b1 reg*/
|
|
<0x00000004 0x00000001 0x00010101>,
|
|
/* mpfe scr noc csr*/
|
|
<0x00000008 0x00000001 0x00010101>;
|
|
bootph-all;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&clkmgr {
|
|
bootph-all;
|
|
};
|
|
|
|
&gpio1 {
|
|
/* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */
|
|
portb: gpio-controller@0{
|
|
sdio_sel {
|
|
gpio-hog;
|
|
gpios = <3 GPIO_ACTIVE_HIGH>;
|
|
output-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c0 {
|
|
reset-names = "i2c";
|
|
};
|
|
|
|
&i2c1 {
|
|
reset-names = "i2c";
|
|
};
|
|
|
|
&i2c2 {
|
|
reset-names = "i2c";
|
|
};
|
|
|
|
&i2c3 {
|
|
reset-names = "i2c";
|
|
};
|
|
|
|
&mmc {
|
|
resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
|
|
};
|
|
|
|
&porta {
|
|
bank-name = "porta";
|
|
};
|
|
|
|
&portb {
|
|
bank-name = "portb";
|
|
};
|
|
|
|
&qspi {
|
|
bootph-all;
|
|
};
|
|
|
|
&rst {
|
|
compatible = "altr,rst-mgr";
|
|
altr,modrst-offset = <0x24>;
|
|
bootph-all;
|
|
};
|
|
|
|
&sdr {
|
|
compatible = "intel,sdr-ctl-agilex5";
|
|
reg = <0x18000000 0x400000>;
|
|
resets = <&rst DDRSCH_RESET>;
|
|
bootph-all;
|
|
};
|
|
|
|
&sysmgr {
|
|
compatible = "altr,sys-mgr", "syscon";
|
|
bootph-all;
|
|
};
|
|
|
|
&uart0 {
|
|
bootph-all;
|
|
};
|
|
|
|
&watchdog0 {
|
|
bootph-all;
|
|
};
|