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2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
97 lines
2.5 KiB
C
97 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cirrus Logic EP93xx PLL support.
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*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <asm/arch/ep93xx.h>
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#include <asm/io.h>
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#include <div64.h>
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/*
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* get_board_sys_clk() should be defined as the input frequency of the PLL.
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*
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* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
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* the specified bus in HZ.
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*/
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/*
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* return the PLL output frequency
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*
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* PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
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* / (X2IPD + 1) / 2^PS
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*/
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static ulong get_PLLCLK(uint32_t *pllreg)
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{
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uint8_t i;
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const uint32_t clkset = readl(pllreg);
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uint64_t rate = get_board_sys_clk();
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rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
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rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
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do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
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for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
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rate >>= 1;
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return (ulong)rate;
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}
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/* return FCLK frequency */
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ulong get_FCLK(void)
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{
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const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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const uint32_t clkset1 = readl(&syscon->clkset1);
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const uint8_t fclk_div =
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fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
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const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
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return fclk_rate;
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}
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/* return HCLK frequency */
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ulong get_HCLK(void)
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{
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const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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const uint32_t clkset1 = readl(&syscon->clkset1);
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const uint8_t hclk_div =
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hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
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const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
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return hclk_rate;
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}
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/* return PCLK frequency */
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ulong get_PCLK(void)
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{
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const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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const uint32_t clkset1 = readl(&syscon->clkset1);
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const uint8_t pclk_div =
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pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
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const ulong pclk_rate = get_HCLK() / pclk_div;
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return pclk_rate;
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}
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/* return UCLK frequency */
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ulong get_UCLK(void)
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{
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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ulong uclk_rate;
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const uint32_t value = readl(&syscon->pwrcnt);
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if (value & SYSCON_PWRCNT_UART_BAUD)
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uclk_rate = get_board_sys_clk();
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else
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uclk_rate = get_board_sys_clk() / 2;
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return uclk_rate;
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}
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