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eced5a7eb4
Due to introducing the new peripheral clock handle functions, use these functions to clean up the duplicated code. Meanwhile, remove unneeded header file include, at91_pmc.h. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixup for arm920t code] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
227 lines
6.2 KiB
C
227 lines
6.2 KiB
C
/*
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* Copyright (C) 2012 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/io.h>
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unsigned int get_chip_id(void)
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{
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/* The 0x40 is the offset of cidr in DBGU */
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return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
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}
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unsigned int get_extension_chip_id(void)
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{
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/* The 0x44 is the offset of exid in DBGU */
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return readl(ATMEL_BASE_DBGU + 0x44);
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}
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unsigned int has_emac1()
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{
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return cpu_is_at91sam9x25();
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}
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unsigned int has_emac0()
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{
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return !(cpu_is_at91sam9g15());
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}
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unsigned int has_lcdc()
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{
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return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
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|| cpu_is_at91sam9x35();
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}
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char *get_cpu_name()
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{
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unsigned int extension_id = get_extension_chip_id();
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if (cpu_is_at91sam9x5()) {
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switch (extension_id) {
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case ARCH_EXID_AT91SAM9G15:
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return "AT91SAM9G15";
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case ARCH_EXID_AT91SAM9G25:
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return "AT91SAM9G25";
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case ARCH_EXID_AT91SAM9G35:
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return "AT91SAM9G35";
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case ARCH_EXID_AT91SAM9X25:
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return "AT91SAM9X25";
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case ARCH_EXID_AT91SAM9X35:
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return "AT91SAM9X35";
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default:
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return "Unknown CPU type";
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}
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} else {
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return "Unknown CPU type";
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}
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}
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void at91_seriald_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
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at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
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at91_periph_clk_enable(ATMEL_ID_SYS);
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}
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void at91_serial0_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
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at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
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at91_periph_clk_enable(ATMEL_ID_USART0);
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}
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void at91_serial1_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
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at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
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at91_periph_clk_enable(ATMEL_ID_USART1);
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}
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void at91_serial2_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
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at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
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at91_periph_clk_enable(ATMEL_ID_USART2);
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}
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void at91_mci_hw_init(void)
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{
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/* Initialize the MCI0 */
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at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
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at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
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at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
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at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
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at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
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at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
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at91_periph_clk_enable(ATMEL_ID_HSMCI0);
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}
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#ifdef CONFIG_ATMEL_SPI
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void at91_spi0_hw_init(unsigned long cs_mask)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
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at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
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at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
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at91_periph_clk_enable(ATMEL_ID_SPI0);
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if (cs_mask & (1 << 0))
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at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
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if (cs_mask & (1 << 1))
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at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
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if (cs_mask & (1 << 2))
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at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
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if (cs_mask & (1 << 3))
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at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
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if (cs_mask & (1 << 4))
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at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
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if (cs_mask & (1 << 5))
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at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
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if (cs_mask & (1 << 6))
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at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
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if (cs_mask & (1 << 7))
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at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
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}
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void at91_spi1_hw_init(unsigned long cs_mask)
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{
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at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
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at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
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at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
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at91_periph_clk_enable(ATMEL_ID_SPI1);
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if (cs_mask & (1 << 0))
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at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
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if (cs_mask & (1 << 1))
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at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
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if (cs_mask & (1 << 2))
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at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
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if (cs_mask & (1 << 3))
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at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
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if (cs_mask & (1 << 4))
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at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
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if (cs_mask & (1 << 5))
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at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
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if (cs_mask & (1 << 6))
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at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
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if (cs_mask & (1 << 7))
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at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
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}
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#endif
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#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
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void at91_uhp_hw_init(void)
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{
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/* Enable VBus on UHP ports */
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at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
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at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
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#if defined(CONFIG_USB_OHCI_NEW)
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/* port C is OHCI only */
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at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
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#endif
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}
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#endif
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#ifdef CONFIG_MACB
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void at91_macb_hw_init(void)
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{
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if (has_emac0()) {
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/* Enable EMAC0 clock */
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at91_periph_clk_enable(ATMEL_ID_EMAC0);
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/* EMAC0 pins setup */
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at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
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at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
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at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
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at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
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at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
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at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
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at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
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at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
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at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
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at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
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}
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if (has_emac1()) {
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/* Enable EMAC1 clock */
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at91_periph_clk_enable(ATMEL_ID_EMAC1);
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/* EMAC1 pins setup */
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at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
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at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
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at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
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at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
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at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
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at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
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at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
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at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
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at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
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at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
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}
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#ifndef CONFIG_RMII
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/* Only emac0 support MII */
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if (has_emac0()) {
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at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
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at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
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at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
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at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
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at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
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at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
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at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
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at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
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}
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#endif
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}
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#endif
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