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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
150 lines
5.1 KiB
C
150 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Chip-specific header file for the AT91SAM9M1x family
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*
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* (C) 2008 Atmel Corporation.
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*
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* Definitions for the SoC:
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* AT91SAM9G45
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*/
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#ifndef AT91SAM9G45_H
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#define AT91SAM9G45_H
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
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#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */
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#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */
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#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */
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#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */
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#define ATMEL_ID_TRNG 6 /* True Random Number Generator */
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#define ATMEL_ID_USART0 7 /* USART 0 */
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#define ATMEL_ID_USART1 8 /* USART 1 */
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#define ATMEL_ID_USART2 9 /* USART 2 */
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#define ATMEL_ID_USART3 10 /* USART 3 */
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#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
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#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */
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#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */
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#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
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#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
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#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */
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#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */
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#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
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#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */
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#define ATMEL_ID_DMA 21 /* DMA Controller */
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#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
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#define ATMEL_ID_LCDC 23 /* LCD Controller */
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#define ATMEL_ID_AC97C 24 /* AC97 Controller */
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#define ATMEL_ID_EMAC 25 /* Ethernet MAC */
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#define ATMEL_ID_ISI 26 /* Image Sensor Interface */
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#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */
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#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
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#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
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#define ATMEL_ID_VDEC 30 /* Video Decoder */
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#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */
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/*
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* User Peripherals physical base addresses.
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*/
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#define ATMEL_BASE_UDPHS 0xfff78000
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#define ATMEL_BASE_TC0 0xfff7c000
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#define ATMEL_BASE_TC1 0xfff7c040
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#define ATMEL_BASE_TC2 0xfff7c080
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#define ATMEL_BASE_MCI0 0xfff80000
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#define ATMEL_BASE_TWI0 0xfff84000
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#define ATMEL_BASE_TWI1 0xfff88000
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#define ATMEL_BASE_USART0 0xfff8c000
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#define ATMEL_BASE_USART1 0xfff90000
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#define ATMEL_BASE_USART2 0xfff94000
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#define ATMEL_BASE_USART3 0xfff98000
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#define ATMEL_BASE_SSC0 0xfff9c000
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#define ATMEL_BASE_SSC1 0xfffa0000
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#define ATMEL_BASE_SPI0 0xfffa4000
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#define ATMEL_BASE_SPI1 0xfffa8000
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#define ATMEL_BASE_AC97C 0xfffac000
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#define ATMEL_BASE_TSC 0xfffb0000
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#define ATMEL_BASE_ISI 0xfffb4000
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#define ATMEL_BASE_PWMC 0xfffb8000
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#define ATMEL_BASE_EMAC 0xfffbc000
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#define ATMEL_BASE_AES 0xfffc0000
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#define ATMEL_BASE_TDES 0xfffc4000
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#define ATMEL_BASE_SHA 0xfffc8000
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#define ATMEL_BASE_TRNG 0xfffcc000
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#define ATMEL_BASE_MCI1 0xfffd0000
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#define ATMEL_BASE_TC3 0xfffd4000
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#define ATMEL_BASE_TC4 0xfffd4040
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#define ATMEL_BASE_TC5 0xfffd4080
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/* Reserved: 0xfffd8000 - 0xffffe1ff */
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/*
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* System Peripherals physical base addresses.
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*/
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#define ATMEL_BASE_SYS 0xffffe200
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#define ATMEL_BASE_ECC 0xffffe200
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#define ATMEL_BASE_DDRSDRC1 0xffffe400
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#define ATMEL_BASE_DDRSDRC0 0xffffe600
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#define ATMEL_BASE_SMC 0xffffe800
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#define ATMEL_BASE_MATRIX 0xffffea00
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#define ATMEL_BASE_DMA 0xffffec00
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#define ATMEL_BASE_DBGU 0xffffee00
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#define ATMEL_BASE_AIC 0xfffff000
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#define ATMEL_BASE_PIOA 0xfffff200
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#define ATMEL_BASE_PIOB 0xfffff400
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#define ATMEL_BASE_PIOC 0xfffff600
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#define ATMEL_BASE_PIOD 0xfffff800
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#define ATMEL_BASE_PIOE 0xfffffa00
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#define ATMEL_BASE_PMC 0xfffffc00
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#define ATMEL_BASE_RSTC 0xfffffd00
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#define ATMEL_BASE_SHDWN 0xfffffd10
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#define ATMEL_BASE_RTT 0xfffffd20
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#define ATMEL_BASE_PIT 0xfffffd30
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#define ATMEL_BASE_WDT 0xfffffd40
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#define ATMEL_BASE_SCKCR 0xfffffd50
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#define ATMEL_BASE_GPBR 0xfffffd60
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#define ATMEL_BASE_RTC 0xfffffdb0
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/* Reserved: 0xfffffdc0 - 0xffffffff */
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/*
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* Internal Memory.
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*/
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#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
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#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
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#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
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#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
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#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */
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#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */
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#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */
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/*
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* External memory
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*/
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#define ATMEL_BASE_CS0 0x10000000
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#define ATMEL_BASE_CS1 0x20000000
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#define ATMEL_BASE_CS2 0x30000000
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#define ATMEL_BASE_CS3 0x40000000
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#define ATMEL_BASE_CS4 0x50000000
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#define ATMEL_BASE_CS5 0x60000000
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#define ATMEL_BASE_CS6 0x70000000
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#define ATMEL_BASE_CS7 0x80000000
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
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/*
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* Other misc defines
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*/
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#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
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#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
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#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
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#define ATMEL_ID_UHP ATMEL_ID_UHPHS
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/*
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* Cpu Name
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*/
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#define ATMEL_CPU_NAME "AT91SAM9G45"
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#endif
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