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	unify arm cache management except for non standard cache as ARM7TDMI Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
		
			
				
	
	
		
			121 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			121 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2002
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|  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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|  *
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|  * See file CREDITS for list of people who contributed to this
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|  * project.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| 
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| #include <common.h>
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| #include <asm/system.h>
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| 
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| #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
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| static void cp_delay (void)
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| {
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| 	volatile int i;
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| 
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| 	/* copro seems to need some delay between reading and writing */
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| 	for (i = 0; i < 100; i++)
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| 		nop();
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| }
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| 
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| /* cache_bit must be either CR_I or CR_C */
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| static void cache_enable(uint32_t cache_bit)
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| {
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| 	uint32_t reg;
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| 
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| 	reg = get_cr();	/* get control reg. */
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| 	cp_delay();
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| 	set_cr(reg | cache_bit);
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| }
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| 
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| /* cache_bit must be either CR_I or CR_C */
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| static void cache_disable(uint32_t cache_bit)
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| {
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| 	uint32_t reg;
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| 
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| 	reg = get_cr();
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| 	cp_delay();
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| 	set_cr(reg & ~cache_bit);
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| }
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| #endif
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| 
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| #ifdef CONFIG_SYS_NO_ICACHE
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| void icache_enable (void)
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| {
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| 	return;
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| }
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| 
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| void icache_disable (void)
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| {
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| 	return;
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| }
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| 
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| int icache_status (void)
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| {
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| 	return 0;					/* always off */
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| }
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| #else
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| void icache_enable(void)
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| {
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| 	cache_enable(CR_I);
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| }
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| 
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| void icache_disable(void)
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| {
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| 	cache_disable(CR_I);
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| }
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| 
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| int icache_status(void)
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| {
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| 	return (get_cr() & CR_I) != 0;
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| }
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| #endif
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| 
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| #ifdef CONFIG_SYS_NO_DCACHE
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| void dcache_enable (void)
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| {
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| 	return;
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| }
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| 
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| void dcache_disable (void)
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| {
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| 	return;
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| }
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| 
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| int dcache_status (void)
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| {
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| 	return 0;					/* always off */
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| }
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| #else
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| void dcache_enable(void)
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| {
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| 	cache_enable(CR_C);
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| }
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| 
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| void dcache_disable(void)
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| {
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| 	cache_disable(CR_C);
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| }
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| 
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| int dcache_status(void)
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| {
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| 	return (get_cr() & CR_C) != 0;
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| }
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| #endif
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