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PCA9450 PMIC supports reading the reset status from the PWRON_STAT register. Bits 7-4 give indication of the PMIC reset cause: - PWRON (BIT7) - Power ON triggered by PMIC_ON_REQ input line, - WDOGB (BIT6) - Boot after cold reset by WDOGB pin (watchdog reset), - SW_RST (BIT5) - Boot after cold reset initiated by the software, - PMIC_RST (BIT4) - Boot after PMIC_RST_B input line trigger. Add support for reading reset status via the sysreset framework in a convenient printable format. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Paul Geurts <paul.geurts@prodrive-technologies.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
197 lines
4.5 KiB
C
197 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <fdtdec.h>
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#include <errno.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#include <linux/printk.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#include <power/pca9450.h>
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#include <sysreset.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct pmic_child_info pmic_children_info[] = {
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/* buck */
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{ .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER},
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{ .prefix = "B", .driver = PCA9450_REGULATOR_DRIVER},
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/* ldo */
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{ .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER},
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{ .prefix = "L", .driver = PCA9450_REGULATOR_DRIVER},
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{ },
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};
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static int pca9450_reg_count(struct udevice *dev)
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{
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return PCA9450_REG_NUM;
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}
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static int pca9450_write(struct udevice *dev, uint reg, const uint8_t *buff,
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int len)
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{
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if (dm_i2c_write(dev, reg, buff, len)) {
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pr_err("write error to device: %p register: %#x!\n", dev, reg);
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return -EIO;
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}
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return 0;
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}
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static int pca9450_read(struct udevice *dev, uint reg, uint8_t *buff,
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int len)
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{
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if (dm_i2c_read(dev, reg, buff, len)) {
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pr_err("read error from device: %p register: %#x!\n", dev, reg);
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return -EIO;
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}
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return 0;
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}
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static int pca9450_bind(struct udevice *dev)
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{
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int children;
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ofnode regulators_node;
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regulators_node = dev_read_subnode(dev, "regulators");
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if (!ofnode_valid(regulators_node)) {
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debug("%s: %s regulators subnode not found!", __func__,
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dev->name);
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return -ENXIO;
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}
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debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
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children = pmic_bind_children(dev, regulators_node,
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pmic_children_info);
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if (!children)
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debug("%s: %s - no child found\n", __func__, dev->name);
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/* Always return success for this device */
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return 0;
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}
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static int pca9450_probe(struct udevice *dev)
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{
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unsigned int reset_ctrl;
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int ret;
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if (CONFIG_IS_ENABLED(SYSRESET)) {
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ret = device_bind_driver_to_node(dev, "pca9450_sysreset",
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"pca9450_sysreset",
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dev_ofnode(dev), NULL);
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if (ret)
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return ret;
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}
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if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset"))
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reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM;
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else
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reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12;
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return pmic_clrsetbits(dev, PCA9450_RESET_CTRL,
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PCA9450_PMIC_RESET_WDOG_B_CFG_MASK, reset_ctrl);
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}
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static struct dm_pmic_ops pca9450_ops = {
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.reg_count = pca9450_reg_count,
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.read = pca9450_read,
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.write = pca9450_write,
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};
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static const struct udevice_id pca9450_ids[] = {
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{ .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, },
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{ .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, },
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{ .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, },
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{ .compatible = "nxp,pca9451a", .data = NXP_CHIP_TYPE_PCA9451A, },
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{ .compatible = "nxp,pca9452", .data = NXP_CHIP_TYPE_PCA9452, },
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{ }
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};
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U_BOOT_DRIVER(pmic_pca9450) = {
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.name = "pca9450 pmic",
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.id = UCLASS_PMIC,
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.of_match = pca9450_ids,
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.bind = pca9450_bind,
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.probe = pca9450_probe,
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.ops = &pca9450_ops,
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};
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#ifdef CONFIG_SYSRESET
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static int pca9450_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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u8 cmd = PCA9450_SW_RST_COLD_RST;
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if (type != SYSRESET_COLD)
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return -EPROTONOSUPPORT;
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if (pmic_write(dev->parent, PCA9450_SW_RST, &cmd, 1)) {
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dev_err(dev, "reset command failed\n");
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} else {
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/* tRESTART is 250ms, delay 300ms just to be sure */
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mdelay(300);
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/* Should not get here, warn if we do */
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dev_warn(dev, "didn't respond to reset command\n");
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}
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return -EINPROGRESS;
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}
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int pca9450_sysreset_get_status(struct udevice *dev, char *buf, int size)
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{
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const char *reason;
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int ret;
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u8 reg;
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ret = pmic_read(dev->parent, PCA9450_PWRON_STAT, ®, 1);
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if (ret)
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return ret;
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switch (reg) {
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case PCA9450_PWRON_STAT_PWRON_MASK:
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reason = "PWRON";
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break;
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case PCA9450_PWRON_STAT_WDOG_MASK:
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reason = "WDOGB";
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break;
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case PCA9450_PWRON_STAT_SW_RST_MASK:
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reason = "SW_RST";
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break;
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case PCA9450_PWRON_STAT_PMIC_RST_MASK:
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reason = "PMIC_RST";
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break;
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default:
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reason = "UNKNOWN";
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break;
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}
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ret = snprintf(buf, size, "Reset Status: %s\n", reason);
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if (ret < 0) {
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dev_err(dev, "Write reset status error (err = %d)\n", ret);
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return -EIO;
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}
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return 0;
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}
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static struct sysreset_ops pca9450_sysreset_ops = {
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.request = pca9450_sysreset_request,
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.get_status = pca9450_sysreset_get_status,
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};
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U_BOOT_DRIVER(pca9450_sysreset) = {
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.name = "pca9450_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &pca9450_sysreset_ops,
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};
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#endif /* CONFIG_SYSRESET */
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