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b1fed50a43
This header includes common register defines and accessor functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*/
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#ifndef __CVMX_REGS_H__
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#define __CVMX_REGS_H__
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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/* General defines */
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#define CVMX_MAX_CORES 48
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/* Maximum # of bits to define core in node */
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#define CVMX_NODE_NO_SHIFT 7
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#define CVMX_NODE_BITS 2 /* Number of bits to define a node */
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#define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
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#define CVMX_NODE_MASK (CVMX_MAX_NODES - 1)
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#define CVMX_NODE_IO_SHIFT 36
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#define CVMX_NODE_MEM_SHIFT 40
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#define CVMX_NODE_IO_MASK ((u64)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
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#define CVMX_MIPS_MAX_CORE_BITS 10 /* Maximum # of bits to define cores */
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#define CVMX_MIPS_MAX_CORES (1 << CVMX_MIPS_MAX_CORE_BITS)
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#define MAX_CORE_TADS 8
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#define CAST_ULL(v) ((unsigned long long)(v))
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#define CASTPTR(type, v) ((type *)(long)(v))
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/* Regs */
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#define CVMX_CIU_PP_RST 0x0001010000000100ULL
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#define CVMX_CIU3_NMI 0x0001010000000160ULL
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#define CVMX_CIU_FUSE 0x00010100000001a0ULL
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#define CVMX_CIU_NMI 0x0001070000000718ULL
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#define CVMX_MIO_BOOT_LOC_CFGX(x) (0x0001180000000080ULL + ((x) & 1) * 8)
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#define MIO_BOOT_LOC_CFG_BASE GENMASK_ULL(27, 3)
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#define MIO_BOOT_LOC_CFG_EN BIT_ULL(31)
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#define CVMX_MIO_BOOT_LOC_ADR 0x0001180000000090ULL
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#define MIO_BOOT_LOC_ADR_ADR GENMASK_ULL(7, 3)
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#define CVMX_MIO_BOOT_LOC_DAT 0x0001180000000098ULL
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#define CVMX_MIO_FUS_DAT2 0x0001180000001410ULL
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#define MIO_FUS_DAT2_NOCRYPTO BIT_ULL(26)
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#define MIO_FUS_DAT2_NOMUL BIT_ULL(27)
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#define MIO_FUS_DAT2_DORM_CRYPTO BIT_ULL(34)
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#define CVMX_MIO_FUS_RCMD 0x0001180000001500ULL
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#define MIO_FUS_RCMD_ADDR GENMASK_ULL(7, 0)
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#define MIO_FUS_RCMD_PEND BIT_ULL(12)
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#define MIO_FUS_RCMD_DAT GENMASK_ULL(23, 16)
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#define CVMX_RNM_CTL_STATUS 0x0001180040000000ULL
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#define RNM_CTL_STATUS_EER_VAL BIT_ULL(9)
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/* turn the variable name into a string */
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#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
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#define CVMX_TMP_STR2(x) #x
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#define CVMX_RDHWRNV(result, regstr) \
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asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
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#define CVMX_SYNCW \
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asm volatile ("syncw\nsyncw\n" : : : "memory")
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/* ToDo: Currently only node = 0 supported */
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static inline u64 csr_rd_node(int node, u64 addr)
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{
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void __iomem *base;
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base = ioremap_nocache(addr, 0x100);
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return ioread64(base);
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}
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static inline u64 csr_rd(u64 addr)
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{
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return csr_rd_node(0, addr);
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}
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static inline void csr_wr_node(int node, u64 addr, u64 val)
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{
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void __iomem *base;
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base = ioremap_nocache(addr, 0x100);
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iowrite64(val, base);
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}
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static inline void csr_wr(u64 addr, u64 val)
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{
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csr_wr_node(0, addr, val);
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}
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/*
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* We need to use the volatile access here, otherwise the IO accessor
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* functions might swap the bytes
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*/
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static inline u64 cvmx_read64_uint64(u64 addr)
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{
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return *(volatile u64 *)addr;
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}
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static inline void cvmx_write64_uint64(u64 addr, u64 val)
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{
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*(volatile u64 *)addr = val;
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}
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static inline u32 cvmx_read64_uint32(u64 addr)
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{
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return *(volatile u32 *)addr;
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}
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static inline void cvmx_write64_uint32(u64 addr, u32 val)
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{
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*(volatile u32 *)addr = val;
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}
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static inline void *cvmx_phys_to_ptr(u64 addr)
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{
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return (void *)CKSEG0ADDR(addr);
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}
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static inline u64 cvmx_ptr_to_phys(void *ptr)
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{
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return virt_to_phys(ptr);
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}
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/**
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* Number of the Core on which the program is currently running.
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*
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* @return core number
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*/
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static inline unsigned int cvmx_get_core_num(void)
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{
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unsigned int core_num;
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CVMX_RDHWRNV(core_num, 0);
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return core_num;
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}
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#endif /* __CVMX_REGS_H__ */
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