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f4df405f0e
With DM_GPIO and DM_MMC translating GPIO_ACTIVE_LOW, any boards using the 'cd-invert' option will no longer need to do this. This patch removes the support for 'invert' from the MMC driver. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Fix warning over when !DM_GPIO] Signed-off-by: Tom Rini <trini@konsulko.com>
238 lines
6.8 KiB
C
238 lines
6.8 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef OMAP_MMC_H_
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#define OMAP_MMC_H_
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#include <mmc.h>
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struct hsmmc {
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#ifndef CONFIG_OMAP34XX
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unsigned int hl_rev;
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unsigned int hl_hwinfo;
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unsigned int hl_sysconfig;
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unsigned char res0[0xf4];
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#endif
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int sysstatus; /* 0x14 */
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unsigned char res2[0x14];
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unsigned int con; /* 0x2C */
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unsigned int pwcnt; /* 0x30 */
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unsigned int dll; /* 0x34 */
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unsigned char res3[0xcc];
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unsigned int blk; /* 0x104 */
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unsigned int arg; /* 0x108 */
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unsigned int cmd; /* 0x10C */
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unsigned int rsp10; /* 0x110 */
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unsigned int rsp32; /* 0x114 */
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unsigned int rsp54; /* 0x118 */
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unsigned int rsp76; /* 0x11C */
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unsigned int data; /* 0x120 */
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unsigned int pstate; /* 0x124 */
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unsigned int hctl; /* 0x128 */
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unsigned int sysctl; /* 0x12C */
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unsigned int stat; /* 0x130 */
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unsigned int ie; /* 0x134 */
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unsigned char res4[0x4];
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unsigned int ac12; /* 0x13C */
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unsigned int capa; /* 0x140 */
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unsigned int capa2; /* 0x144 */
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unsigned char res5[0xc];
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unsigned int admaes; /* 0x154 */
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unsigned int admasal; /* 0x158 */
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};
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struct omap_hsmmc_plat {
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struct mmc_config cfg;
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struct hsmmc *base_addr;
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struct mmc *mmc;
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u32 controller_flags;
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const char *hw_rev;
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};
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/*
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* OMAP HS MMC Bit definitions
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*/
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#define MADMA_EN (0x1 << 0)
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#define MMC_SOFTRESET (0x1 << 1)
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#define RESETDONE (0x1 << 0)
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#define NOOPENDRAIN (0x0 << 0)
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#define OPENDRAIN (0x1 << 0)
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#define OD (0x1 << 0)
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#define INIT_NOINIT (0x0 << 1)
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#define INIT_INITSTREAM (0x1 << 1)
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#define HR_NOHOSTRESP (0x0 << 2)
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#define STR_BLOCK (0x0 << 3)
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#define MODE_FUNC (0x0 << 4)
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#define DW8_1_4BITMODE (0x0 << 5)
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#define MIT_CTO (0x0 << 6)
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#define CDP_ACTIVEHIGH (0x0 << 7)
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#define WPP_ACTIVEHIGH (0x0 << 8)
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#define RESERVED_MASK (0x3 << 9)
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#define CTPL_MMC_SD (0x0 << 11)
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#define DDR (0x1 << 19)
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#define DMA_MASTER (0x1 << 20)
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#define BLEN_512BYTESLEN (0x200 << 0)
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#define NBLK_STPCNT (0x0 << 16)
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#define DE_ENABLE (0x1 << 0)
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#define BCE_ENABLE (0x1 << 1)
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#define ACEN_ENABLE (0x1 << 2)
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#define DDIR_OFFSET (4)
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#define DDIR_MASK (0x1 << 4)
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#define DDIR_WRITE (0x0 << 4)
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#define DDIR_READ (0x1 << 4)
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#define MSBS_SGLEBLK (0x0 << 5)
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#define MSBS_MULTIBLK (0x1 << 5)
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#define RSP_TYPE_OFFSET (16)
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#define RSP_TYPE_MASK (0x3 << 16)
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#define RSP_TYPE_NORSP (0x0 << 16)
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#define RSP_TYPE_LGHT136 (0x1 << 16)
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#define RSP_TYPE_LGHT48 (0x2 << 16)
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#define RSP_TYPE_LGHT48B (0x3 << 16)
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#define CCCE_NOCHECK (0x0 << 19)
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#define CCCE_CHECK (0x1 << 19)
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#define CICE_NOCHECK (0x0 << 20)
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#define CICE_CHECK (0x1 << 20)
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#define DP_OFFSET (21)
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#define DP_MASK (0x1 << 21)
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#define DP_NO_DATA (0x0 << 21)
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#define DP_DATA (0x1 << 21)
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#define CMD_TYPE_NORMAL (0x0 << 22)
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#define INDEX_OFFSET (24)
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#define INDEX_MASK (0x3f << 24)
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#define INDEX(i) (i << 24)
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#define DATI_MASK (0x1 << 1)
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#define CMDI_MASK (0x1 << 0)
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#define DTW_1_BITMODE (0x0 << 1)
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#define DTW_4_BITMODE (0x1 << 1)
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#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
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#define SDBP_PWROFF (0x0 << 8)
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#define SDBP_PWRON (0x1 << 8)
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#define SDVS_MASK (0x7 << 9)
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#define SDVS_1V8 (0x5 << 9)
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#define SDVS_3V0 (0x6 << 9)
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#define SDVS_3V3 (0x7 << 9)
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#define DMA_SELECT (0x2 << 3)
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#define ICE_MASK (0x1 << 0)
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#define ICE_STOP (0x0 << 0)
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#define ICS_MASK (0x1 << 1)
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#define ICS_NOTREADY (0x0 << 1)
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#define ICE_OSCILLATE (0x1 << 0)
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#define CEN_MASK (0x1 << 2)
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#define CEN_ENABLE (0x1 << 2)
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#define CLKD_OFFSET (6)
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#define CLKD_MASK (0x3FF << 6)
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#define DTO_MASK (0xF << 16)
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#define DTO_15THDTO (0xE << 16)
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#define SOFTRESETALL (0x1 << 24)
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#define CC_MASK (0x1 << 0)
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#define TC_MASK (0x1 << 1)
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#define BWR_MASK (0x1 << 4)
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#define BRR_MASK (0x1 << 5)
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#define ERRI_MASK (0x1 << 15)
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#define IE_CC (0x01 << 0)
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#define IE_TC (0x01 << 1)
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#define IE_BWR (0x01 << 4)
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#define IE_BRR (0x01 << 5)
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#define IE_CTO (0x01 << 16)
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#define IE_CCRC (0x01 << 17)
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#define IE_CEB (0x01 << 18)
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#define IE_CIE (0x01 << 19)
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#define IE_DTO (0x01 << 20)
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#define IE_DCRC (0x01 << 21)
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#define IE_DEB (0x01 << 22)
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#define IE_ADMAE (0x01 << 25)
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#define IE_CERR (0x01 << 28)
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#define IE_BADA (0x01 << 29)
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#define VS33_3V3SUP BIT(24)
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#define VS30_3V0SUP BIT(25)
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#define VS18_1V8SUP BIT(26)
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#define AC12_ET BIT(22)
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#define AC12_V1V8_SIGEN BIT(19)
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#define AC12_SCLK_SEL BIT(23)
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#define AC12_UHSMC_MASK (7 << 16)
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#define AC12_UHSMC_DDR50 (4 << 16)
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#define AC12_UHSMC_SDR104 (3 << 16)
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#define AC12_UHSMC_SDR50 (2 << 16)
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#define AC12_UHSMC_SDR25 (1 << 16)
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#define AC12_UHSMC_SDR12 (0 << 16)
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#define AC12_UHSMC_RES (0x7 << 16)
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/* Driver definitions */
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#define MMCSD_SECTOR_SIZE 512
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#define MMC_CARD 0
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#define SD_CARD 1
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#define BYTE_MODE 0
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#define SECTOR_MODE 1
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#define CLK_INITSEQ 0
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#define CLK_400KHZ 1
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#define CLK_MISC 2
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#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
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#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
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#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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/* Clock Configurations and Macros */
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#ifdef CONFIG_OMAP54XX
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#define MMC_CLOCK_REFERENCE 192 /* MHz */
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#else
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#define MMC_CLOCK_REFERENCE 96 /* MHz */
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#endif
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/* DLL */
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#define DLL_SWT BIT(20)
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#define DLL_FORCE_SR_C_SHIFT 13
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#define DLL_FORCE_SR_C_MASK 0x7f
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#define DLL_FORCE_VALUE BIT(12)
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#define DLL_CALIB BIT(1)
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#define MAX_PHASE_DELAY 0x7c
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/* CAPA2 */
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#define CAPA2_TSDR50 BIT(13)
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#define mmc_reg_out(addr, mask, val)\
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writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
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#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
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IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
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IE_BRR | IE_BWR | IE_TC | IE_CC)
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#define CON_CLKEXTFREE BIT(16)
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#define CON_PADEN BIT(15)
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#define PSTATE_CLEV BIT(24)
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#define PSTATE_DLEV (0xF << 20)
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#define PSTATE_DLEV_DAT0 (0x1 << 20)
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int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
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int wp_gpio);
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void vmmc_pbias_config(uint voltage);
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void board_mmc_poweron_ldo(uint voltage);
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#endif /* OMAP_MMC_H_ */
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