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	Add DM and DT probing support to iMX watchdog driver. This should allow boards to move over to this driver, enable SYSRESET_WATCHDOG to handle cpu_reset() if required. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
		
			
				
	
	
		
			152 lines
		
	
	
		
			3.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			152 lines
		
	
	
		
			3.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * watchdog.c - driver for i.mx on-chip watchdog
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|  *
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|  * Licensed under the GPL-2 or later.
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|  */
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| 
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| #include <common.h>
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| #include <dm.h>
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| #include <asm/io.h>
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| #include <wdt.h>
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| #include <watchdog.h>
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| #include <asm/arch/imx-regs.h>
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| #ifdef CONFIG_FSL_LSCH2
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| #include <asm/arch/immap_lsch2.h>
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| #endif
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| #include <fsl_wdog.h>
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| 
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| static void imx_watchdog_expire_now(struct watchdog_regs *wdog)
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| {
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| 	clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
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| 
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| 	writew(0x5555, &wdog->wsr);
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| 	writew(0xaaaa, &wdog->wsr);	/* load minimum 1/2 second timeout */
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| 	while (1) {
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| 		/*
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| 		 * spin for .5 seconds before reset
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| 		 */
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| 	}
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| }
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| 
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| #if !defined(CONFIG_IMX_WATCHDOG) || \
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|     (defined(CONFIG_IMX_WATCHDOG) && !CONFIG_IS_ENABLED(WDT))
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| void __attribute__((weak)) reset_cpu(ulong addr)
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| {
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| 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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| 
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| 	imx_watchdog_expire_now(wdog);
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| }
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| #endif
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| 
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| #if defined(CONFIG_IMX_WATCHDOG)
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| static void imx_watchdog_reset(struct watchdog_regs *wdog)
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| {
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| #ifndef CONFIG_WATCHDOG_RESET_DISABLE
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| 	writew(0x5555, &wdog->wsr);
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| 	writew(0xaaaa, &wdog->wsr);
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| #endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
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| }
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| 
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| static void imx_watchdog_init(struct watchdog_regs *wdog)
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| {
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| 	u16 timeout;
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| 
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| 	/*
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| 	 * The timer watchdog can be set between
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| 	 * 0.5 and 128 Seconds. If not defined
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| 	 * in configuration file, sets 128 Seconds
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| 	 */
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| #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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| #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
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| #endif
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| 	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
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| #ifdef CONFIG_FSL_LSCH2
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| 	writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr);
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| #else
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| 	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
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| 		WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
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| #endif /* CONFIG_FSL_LSCH2*/
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| 	imx_watchdog_reset(wdog);
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| }
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| 
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| #if !CONFIG_IS_ENABLED(WDT)
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| void hw_watchdog_reset(void)
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| {
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| 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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| 
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| 	imx_watchdog_reset(wdog);
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| }
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| 
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| void hw_watchdog_init(void)
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| {
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| 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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| 
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| 	imx_watchdog_init(wdog);
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| }
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| #else
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| struct imx_wdt_priv {
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| 	void __iomem *base;
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| };
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| 
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| static int imx_wdt_reset(struct udevice *dev)
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| {
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| 	struct imx_wdt_priv *priv = dev_get_priv(dev);
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| 
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| 	imx_watchdog_reset(priv->base);
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| 
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| 	return 0;
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| }
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| 
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| static int imx_wdt_expire_now(struct udevice *dev, ulong flags)
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| {
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| 	struct imx_wdt_priv *priv = dev_get_priv(dev);
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| 
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| 	imx_watchdog_expire_now(priv->base);
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| 	hang();
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| 
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| 	return 0;
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| }
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| 
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| static int imx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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| {
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| 	struct imx_wdt_priv *priv = dev_get_priv(dev);
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| 
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| 	imx_watchdog_init(priv->base);
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| 
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| 	return 0;
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| }
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| 
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| static int imx_wdt_probe(struct udevice *dev)
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| {
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| 	struct imx_wdt_priv *priv = dev_get_priv(dev);
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| 
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| 	priv->base = dev_read_addr_ptr(dev);
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| 	if (!priv->base)
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| 		return -ENOENT;
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| 
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| 	return 0;
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| }
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| 
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| static const struct wdt_ops imx_wdt_ops = {
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| 	.start		= imx_wdt_start,
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| 	.reset		= imx_wdt_reset,
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| 	.expire_now	= imx_wdt_expire_now,
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| };
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| 
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| static const struct udevice_id imx_wdt_ids[] = {
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| 	{ .compatible = "fsl,imx21-wdt" },
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| 	{}
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| };
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| 
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| U_BOOT_DRIVER(imx_wdt) = {
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| 	.name		= "imx_wdt",
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| 	.id		= UCLASS_WDT,
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| 	.of_match	= imx_wdt_ids,
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| 	.probe		= imx_wdt_probe,
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| 	.ops		= &imx_wdt_ops,
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| 	.priv_auto_alloc_size = sizeof(struct imx_wdt_priv),
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| 	.flags		= DM_FLAG_PRE_RELOC,
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| };
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| #endif
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| #endif
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