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5d88902401
The EFI subsystem accesses the real time clock and is enabled by default. So we should drop any CONFIG_CMD_DATE dependency from the real time clock drivers. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
161 lines
4.0 KiB
C
161 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* based on a the Linux rtc-x1207.c driver which is:
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* Copyright 2004 Karen Spearel
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* Copyright 2005 Alessandro Zummo
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*
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* Information and datasheet:
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* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
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*/
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/*
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* Date & Time support for Xicor/Intersil X1205 RTC
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*/
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/* #define DEBUG */
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#include <common.h>
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#include <command.h>
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#include <rtc.h>
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#include <i2c.h>
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#define CCR_SEC 0
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#define CCR_MIN 1
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#define CCR_HOUR 2
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#define CCR_MDAY 3
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#define CCR_MONTH 4
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#define CCR_YEAR 5
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#define CCR_WDAY 6
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#define CCR_Y2K 7
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#define X1205_REG_SR 0x3F /* status register */
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#define X1205_REG_Y2K 0x37
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#define X1205_REG_DW 0x36
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#define X1205_REG_YR 0x35
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#define X1205_REG_MO 0x34
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#define X1205_REG_DT 0x33
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#define X1205_REG_HR 0x32
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#define X1205_REG_MN 0x31
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#define X1205_REG_SC 0x30
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#define X1205_REG_DTR 0x13
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#define X1205_REG_ATR 0x12
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#define X1205_REG_INT 0x11
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#define X1205_REG_0 0x10
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#define X1205_REG_Y2K1 0x0F
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#define X1205_REG_DWA1 0x0E
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#define X1205_REG_YRA1 0x0D
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#define X1205_REG_MOA1 0x0C
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#define X1205_REG_DTA1 0x0B
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#define X1205_REG_HRA1 0x0A
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#define X1205_REG_MNA1 0x09
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#define X1205_REG_SCA1 0x08
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#define X1205_REG_Y2K0 0x07
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#define X1205_REG_DWA0 0x06
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#define X1205_REG_YRA0 0x05
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#define X1205_REG_MOA0 0x04
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#define X1205_REG_DTA0 0x03
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#define X1205_REG_HRA0 0x02
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#define X1205_REG_MNA0 0x01
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#define X1205_REG_SCA0 0x00
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#define X1205_CCR_BASE 0x30 /* Base address of CCR */
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#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
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#define X1205_SR_RTCF 0x01 /* Clock failure */
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#define X1205_SR_WEL 0x02 /* Write Enable Latch */
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#define X1205_SR_RWEL 0x04 /* Register Write Enable */
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#define X1205_DTR_DTR0 0x01
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#define X1205_DTR_DTR1 0x02
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#define X1205_DTR_DTR2 0x04
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#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
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static void rtc_write(int reg, u8 val)
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{
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i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
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}
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/*
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* In the routines that deal directly with the x1205 hardware, we use
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* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
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* Epoch is initialized as 2000. Time is set to UTC.
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*/
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int rtc_get(struct rtc_time *tm)
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{
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u8 buf[8];
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i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
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debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
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"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
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__FUNCTION__,
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buf[0], buf[1], buf[2], buf[3],
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buf[4], buf[5], buf[6], buf[7]);
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tm->tm_sec = bcd2bin(buf[CCR_SEC]);
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tm->tm_min = bcd2bin(buf[CCR_MIN]);
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tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
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tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
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tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
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tm->tm_year = bcd2bin(buf[CCR_YEAR])
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+ (bcd2bin(buf[CCR_Y2K]) * 100);
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tm->tm_wday = buf[CCR_WDAY];
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debug("%s: tm is secs=%d, mins=%d, hours=%d, "
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"mday=%d, mon=%d, year=%d, wday=%d\n",
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__FUNCTION__,
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tm->tm_sec, tm->tm_min, tm->tm_hour,
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tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
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return 0;
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}
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int rtc_set(struct rtc_time *tm)
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{
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int i;
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u8 buf[8];
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debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
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tm->tm_hour, tm->tm_min, tm->tm_sec);
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buf[CCR_SEC] = bin2bcd(tm->tm_sec);
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buf[CCR_MIN] = bin2bcd(tm->tm_min);
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/* set hour and 24hr bit */
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buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
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buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
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/* month, 1 - 12 */
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buf[CCR_MONTH] = bin2bcd(tm->tm_mon);
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/* year, since the rtc epoch*/
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buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
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buf[CCR_WDAY] = tm->tm_wday & 0x07;
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buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);
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/* this sequence is required to unlock the chip */
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rtc_write(X1205_REG_SR, X1205_SR_WEL);
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rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
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/* write register's data */
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for (i = 0; i < 8; i++)
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rtc_write(X1205_CCR_BASE + i, buf[i]);
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rtc_write(X1205_REG_SR, 0);
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return 0;
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}
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void rtc_reset(void)
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{
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/*
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* Nothing to do
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*/
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}
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