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386fca6896
This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
81 lines
1.8 KiB
C
81 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2024 Intel Corporation. All rights reserved
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*/
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#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
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#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
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/* PER0MODRST */
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#define EMAC0_RESET 0
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#define EMAC1_RESET 1
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#define EMAC2_RESET 2
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#define USB0_RESET 3
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#define USB1_RESET 4
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#define NAND_RESET 5
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#define COMBOPHY_RESET 6
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#define SDMMC_RESET 7
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#define EMAC0_OCP_RESET 8
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#define EMAC1_OCP_RESET 9
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#define EMAC2_OCP_RESET 10
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#define USB0_OCP_RESET 11
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#define USB1_OCP_RESET 12
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#define NAND_OCP_RESET 13
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/* 14 is empty */
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#define SDMMC_OCP_RESET 15
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#define DMA_RESET 16
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#define SPIM0_RESET 17
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#define SPIM1_RESET 18
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#define SPIS0_RESET 19
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#define SPIS1_RESET 20
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#define DMA_OCP_RESET 21
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#define EMAC_PTP_RESET 22
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/* 23 is empty*/
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#define DMAIF0_RESET 24
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#define DMAIF1_RESET 25
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#define DMAIF2_RESET 26
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#define DMAIF3_RESET 27
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#define DMAIF4_RESET 28
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#define DMAIF5_RESET 29
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#define DMAIF6_RESET 30
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#define DMAIF7_RESET 31
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/* PER1MODRST */
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#define WATCHDOG0_RESET 32
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#define WATCHDOG1_RESET 33
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#define WATCHDOG2_RESET 34
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#define WATCHDOG3_RESET 35
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#define L4SYSTIMER0_RESET 36
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#define L4SYSTIMER1_RESET 37
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#define SPTIMER0_RESET 38
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#define SPTIMER1_RESET 39
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#define I2C0_RESET 40
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#define I2C1_RESET 41
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#define I2C2_RESET 42
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#define I2C3_RESET 43
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#define I2C4_RESET 44
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#define I3C0_RESET 45
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#define I3C1_RESET 46
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/* 47 is empty */
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#define UART0_RESET 48
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#define UART1_RESET 49
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/* 50-55 is empty */
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#define GPIO0_RESET 56
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#define GPIO1_RESET 57
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#define WATCHDOG4_RESET 58
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/* 59-63 is empty */
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/* BRGMODRST */
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#define SOC2FPGA_RESET 64
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#define LWHPS2FPGA_RESET 65
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#define FPGA2SOC_RESET 66
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#define F2SSDRAM_RESET 67
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/* 68-69 is empty */
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#define DDRSCH_RESET 70
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/* 71-95 is empty */
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/* DBGMODRST */
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#define DBG_RESET 192
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#endif
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