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Add pinctrl support for Exynos850 SoC. It was mostly extracted from corresponding Linux kernel code [1]. Power down modes and external interrupt data were removed while converting the code for U-Boot, but everything else was kept almost unchanged. [1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 Linaro Ltd.
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* Author: Sam Protsenko <semen.protsenko@linaro.org>
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*
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* Exynos850 pinctrl driver.
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*/
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include "pinctrl-exynos.h"
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#define EXYNOS850_PIN_BANK(pins, reg, id) \
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{ \
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.type = &exynos850_bank_type, \
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.offset = reg, \
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.nr_pins = pins, \
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.name = id \
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}
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/* CON, DAT, PUD, DRV */
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static const struct samsung_pin_bank_type exynos850_bank_type = {
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.fld_width = { 4, 1, 4, 4, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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static const struct pinctrl_ops exynos850_pinctrl_ops = {
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.set_state = exynos_pinctrl_set_state
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};
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/* pin banks of exynos850 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos850_pin_banks0[] = {
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EXYNOS850_PIN_BANK(8, 0x000, "gpa0"),
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EXYNOS850_PIN_BANK(8, 0x020, "gpa1"),
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EXYNOS850_PIN_BANK(8, 0x040, "gpa2"),
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EXYNOS850_PIN_BANK(8, 0x060, "gpa3"),
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EXYNOS850_PIN_BANK(4, 0x080, "gpa4"),
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EXYNOS850_PIN_BANK(3, 0x0a0, "gpq0"),
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};
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/* pin banks of exynos850 pin-controller 1 (CMGP) */
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static const struct samsung_pin_bank_data exynos850_pin_banks1[] = {
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EXYNOS850_PIN_BANK(1, 0x000, "gpm0"),
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EXYNOS850_PIN_BANK(1, 0x020, "gpm1"),
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EXYNOS850_PIN_BANK(1, 0x040, "gpm2"),
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EXYNOS850_PIN_BANK(1, 0x060, "gpm3"),
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EXYNOS850_PIN_BANK(1, 0x080, "gpm4"),
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EXYNOS850_PIN_BANK(1, 0x0a0, "gpm5"),
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EXYNOS850_PIN_BANK(1, 0x0c0, "gpm6"),
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EXYNOS850_PIN_BANK(1, 0x0e0, "gpm7"),
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};
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/* pin banks of exynos850 pin-controller 2 (AUD) */
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static const struct samsung_pin_bank_data exynos850_pin_banks2[] = {
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EXYNOS850_PIN_BANK(5, 0x000, "gpb0"),
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EXYNOS850_PIN_BANK(5, 0x020, "gpb1"),
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};
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/* pin banks of exynos850 pin-controller 3 (HSI) */
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static const struct samsung_pin_bank_data exynos850_pin_banks3[] = {
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EXYNOS850_PIN_BANK(6, 0x000, "gpf2"),
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};
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/* pin banks of exynos850 pin-controller 4 (CORE) */
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static const struct samsung_pin_bank_data exynos850_pin_banks4[] = {
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EXYNOS850_PIN_BANK(4, 0x000, "gpf0"),
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EXYNOS850_PIN_BANK(8, 0x020, "gpf1"),
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};
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/* pin banks of exynos850 pin-controller 5 (PERI) */
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static const struct samsung_pin_bank_data exynos850_pin_banks5[] = {
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EXYNOS850_PIN_BANK(2, 0x000, "gpg0"),
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EXYNOS850_PIN_BANK(6, 0x020, "gpp0"),
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EXYNOS850_PIN_BANK(4, 0x040, "gpp1"),
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EXYNOS850_PIN_BANK(4, 0x060, "gpp2"),
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EXYNOS850_PIN_BANK(8, 0x080, "gpg1"),
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EXYNOS850_PIN_BANK(8, 0x0a0, "gpg2"),
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EXYNOS850_PIN_BANK(1, 0x0c0, "gpg3"),
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EXYNOS850_PIN_BANK(3, 0x0e0, "gpc0"),
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EXYNOS850_PIN_BANK(6, 0x100, "gpc1"),
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};
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static const struct samsung_pin_ctrl exynos850_pin_ctrl[] = {
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{
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/* pin-controller instance 0 ALIVE data */
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.pin_banks = exynos850_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks0),
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}, {
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/* pin-controller instance 1 CMGP data */
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.pin_banks = exynos850_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks1),
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}, {
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/* pin-controller instance 2 AUD data */
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.pin_banks = exynos850_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks2),
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}, {
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/* pin-controller instance 3 HSI data */
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.pin_banks = exynos850_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks3),
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}, {
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/* pin-controller instance 4 CORE data */
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.pin_banks = exynos850_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks4),
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}, {
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/* pin-controller instance 5 PERI data */
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.pin_banks = exynos850_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks5),
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},
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{/* list terminator */}
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};
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static const struct udevice_id exynos850_pinctrl_ids[] = {
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{ .compatible = "samsung,exynos850-pinctrl",
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.data = (ulong)exynos850_pin_ctrl },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_exynos850) = {
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.name = "pinctrl_exynos850",
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.id = UCLASS_PINCTRL,
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.of_match = exynos850_pinctrl_ids,
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.priv_auto = sizeof(struct exynos_pinctrl_priv),
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.ops = &exynos850_pinctrl_ops,
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.probe = exynos_pinctrl_probe,
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};
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