Bin Meng e61a2687b3 x86: braswell: Add microcode for B0/C0/D0 stepping SoC ...

This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

2017-09-16 14:57:44 +08:00

..

m01406c440a.dtsi

x86: braswell: Add microcode for B0/C0/D0 stepping SoC

2017-09-16 14:57:44 +08:00

m01406c2220.dtsi

x86: braswell: Add microcode for B0/C0/D0 stepping SoC

2017-09-16 14:57:44 +08:00

m01406c3363.dtsi

x86: braswell: Add microcode for B0/C0/D0 stepping SoC

2017-09-16 14:57:44 +08:00

m12206a7_00000029.dtsi

x86: ivybridge: Update the microcode

2014-12-18 17:26:05 -07:00

m12306a2_00000008.dtsi

x86: ivybridge: Add microcode blobs for all the steppings

2016-01-13 12:20:15 +08:00

m12306a4_00000007.dtsi

x86: ivybridge: Add microcode blobs for all the steppings

2016-01-13 12:20:15 +08:00

m12306a5_00000007.dtsi

x86: ivybridge: Add microcode blobs for all the steppings

2016-01-13 12:20:15 +08:00

m12306a8_00000010.dtsi

x86: ivybridge: Add microcode blobs for all the steppings

2016-01-13 12:20:15 +08:00

m12306a9_0000001b.dtsi

x86: ivybridge: Update the microcode

2014-12-18 17:26:05 -07:00

m7240651_0000001c.dtsi

x86: broadwell: Add a few microcode files

2016-03-17 10:27:23 +08:00

m0130673325.dtsi

x86: baytrail: Update to latest microcode

2016-05-23 15:24:24 +08:00

m0130679907.dtsi

x86: baytrail: Update to latest microcode

2016-05-23 15:24:24 +08:00

m0220661105_cv.dtsi

x86: Integrate Tunnel Creek processor microcode

2014-12-18 17:26:05 -07:00

m0230671117.dtsi

x86: Add microcode for BayTrail-I B0 stepping

2015-08-05 08:42:39 -06:00

mc0306d4_00000018.dtsi

x86: broadwell: Add a few microcode files

2016-03-17 10:27:23 +08:00