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a245aece2a
Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
36 lines
759 B
C
36 lines
759 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Qualcomm common pin control data.
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*
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* Copyright (C) 2023 Linaro Ltd.
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*/
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#ifndef _QCOM_GPIO_H_
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#define _QCOM_GPIO_H_
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#include <asm/types.h>
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#include <stdbool.h>
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struct msm_pin_data {
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int pin_count;
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const unsigned int *pin_offsets;
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/* Index of first special pin, these are ignored for now */
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unsigned int special_pins_start;
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};
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static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
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{
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u32 out = (selector * 0x1000);
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if (offs)
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return out + offs[selector];
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return out;
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}
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static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin)
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{
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return pindata->special_pins_start && pin >= pindata->special_pins_start;
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}
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#endif /* _QCOM_GPIO_H_ */
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