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7d7bb99e22
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com>
8 lines
188 B
C
8 lines
188 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _ALLEYCAT5_SOC_H
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#define _ALLEYCAT5_SOC_H
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void soc_print_device_info(void);
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void soc_print_clock_info(void);
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#endif /* _ALLEYCAT5_SOC_H */
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