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20a0ce574d
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60 lines
2.1 KiB
Plaintext
60 lines
2.1 KiB
Plaintext
config K3_LOAD_SYSFW
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bool
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config K3_QOS
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bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs"
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default y if SOC_K3_AM62A7
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help
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This option enables the R5 SPL to apply QoS settings for various
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HW controllers inside the TI K3 SoCs. The files for QoS settings are
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generated from Sysconfig and k3-resource-partitioning tools.
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config K3_SYSFW_IMAGE_NAME
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string "File name of SYSFW firmware and configuration blob"
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depends on K3_LOAD_SYSFW
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default "sysfw.itb"
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help
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Filename of the combined System Firmware and configuration image tree
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blob to be loaded when booting from a filesystem.
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config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
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hex "MMC sector to load SYSFW firmware and configuration blob from"
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depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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default 0x3600
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help
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Address on the MMC to load the combined System Firmware and
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configuration image tree blob from, when the MMC is being used
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in raw mode. Units: MMC sectors (1 sector = 512 bytes).
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config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
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hex "MMC partition to load SYSFW firmware and configuration blob from"
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depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
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default 2
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help
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Partition on the MMC to the combined System Firmware and configuration
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image tree blob from, when the MMC is being used in raw mode.
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config K3_SYSFW_IMAGE_SIZE_MAX
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int "Amount of memory dynamically allocated for loading SYSFW blob"
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depends on K3_LOAD_SYSFW
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default 280000
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help
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Amount of memory (in bytes) reserved through dynamic allocation at
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runtime for loading the combined System Firmware and configuration image
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tree blob. Keep it as tight as possible, as this directly affects the
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overall SPL memory footprint.
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config K3_SYSFW_IMAGE_SPI_OFFS
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hex "SPI offset of SYSFW firmware and configuration blob"
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depends on K3_LOAD_SYSFW
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default 0x6C0000
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help
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Offset of the combined System Firmware and configuration image tree
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blob to be loaded when booting from a SPI flash memory.
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config SYS_K3_SPL_ATF
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bool "Start Cortex-A from SPL"
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help
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Enabling this will try to start Cortex-A (typically with ATF)
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after SPL from R5.
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