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4c5f03ef3f
The cpu_sun50i_h6.h header file defined the base addresses for quite some peripherals of the Allwinner H6 and related CPUs, even though we now only use a fraction of that. Most of the addresses are now either read from the DT, or were never used in U-Boot in the first place. Removed the ones that are not used in the whole of the U-Boot source. to make it clear that this file only contains addresses that are needed for the SPL operation. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CPU_SUN50I_H6_H
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#define _SUNXI_CPU_SUN50I_H6_H
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#define SUNXI_SRAMC_BASE 0x03000000
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#define SUNXI_CCM_BASE 0x03001000
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/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
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#define SUNXI_SIDC_BASE 0x03006000
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#define SUNXI_SID_BASE 0x03006200
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#define SUNXI_TIMER_BASE 0x03009000
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#define SUNXI_GIC400_BASE 0x03020000
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#ifdef CONFIG_MACH_SUN50I_H6
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#define SUNXI_DRAM_COM_BASE 0x04002000
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#define SUNXI_DRAM_CTL0_BASE 0x04003000
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#define SUNXI_DRAM_PHY0_BASE 0x04005000
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#endif
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#define SUNXI_NFC_BASE 0x04011000
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#define SUNXI_MMC0_BASE 0x04020000
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#define SUNXI_MMC1_BASE 0x04021000
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#define SUNXI_MMC2_BASE 0x04022000
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#ifdef CONFIG_MACH_SUN50I_H616
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#define SUNXI_DRAM_COM_BASE 0x047FA000
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#define SUNXI_DRAM_CTL0_BASE 0x047FB000
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#define SUNXI_DRAM_PHY0_BASE 0x04800000
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#endif
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#define SUNXI_TWI0_BASE 0x05002000
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#define SUNXI_TWI1_BASE 0x05002400
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#define SUNXI_TWI2_BASE 0x05002800
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#define SUNXI_TWI3_BASE 0x05002C00
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#define SUNXI_HDMI_BASE 0x06000000
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#define SUNXI_RTC_BASE 0x07000000
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#define SUNXI_R_CPUCFG_BASE 0x07000400
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#define SUNXI_PRCM_BASE 0x07010000
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#define SUNXI_R_WDOG_BASE 0x07020400
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#define SUNXI_R_TWI_BASE 0x07081400
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#ifndef __ASSEMBLY__
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void sunxi_board_init(void);
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void sunxi_reset(void);
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int sunxi_get_sid(unsigned int *sid);
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#endif
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#endif /* _SUNXI_CPU_SUN9I_H */
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