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https://source.denx.de/u-boot/u-boot.git
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131 lines
2.7 KiB
C
131 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#ifndef CONFIG_ARMV7_NONSEC
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#error " Deep sleep needs non-secure mode support. "
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#else
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#include <asm/secure.h>
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#endif
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#include <asm/armv7.h>
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#if defined(CONFIG_ARCH_LS1021A)
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#include <asm/arch/immap_ls102xa.h>
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#endif
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#include "sleep.h"
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#ifdef CONFIG_U_QE
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#include <fsl_qe.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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void __weak board_mem_sleep_setup(void)
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{
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}
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void __weak board_sleep_prepare(void)
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{
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}
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bool is_warm_boot(void)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
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return 1;
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return 0;
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}
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void fsl_dp_disable_console(void)
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{
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gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
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}
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/*
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* When wakeup from deep sleep, the first 128 bytes space
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* will be used to do DDR training which corrupts the data
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* in there. This function will restore them.
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*/
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static void dp_ddr_restore(void)
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{
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u64 *src, *dst;
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int i;
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
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/* get the address of ddr date from SPARECR3 */
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src = (u64 *)in_le32(&scfg->sparecr[2]);
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dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
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for (i = 0; i < DDR_BUFF_LEN / 8; i++)
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*dst++ = *src++;
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}
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#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
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void ls1_psci_resume_fixup(void)
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{
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u32 tmp;
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef QIXIS_BASE
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void *qixis_base = (void *)QIXIS_BASE;
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/* Pull on PCIe RST# */
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out_8(qixis_base + QIXIS_RST_FORCE_3, 0);
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/* disable deep sleep signals in FPGA */
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tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
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tmp &= ~QIXIS_PWR_CTL2_PCTL;
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out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
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#endif
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/* Disable wakeup interrupt during deep sleep */
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out_be32(&scfg->pmcintecr, 0);
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/* Clear PMC interrupt status */
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out_be32(&scfg->pmcintsr, 0xffffffff);
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/* Disable Warm Device Reset */
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tmp = in_be32(&scfg->dpslpcr);
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tmp &= ~SCFG_DPSLPCR_WDRR_EN;
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out_be32(&scfg->dpslpcr, tmp);
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}
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#endif
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static void dp_resume_prepare(void)
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{
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dp_ddr_restore();
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board_sleep_prepare();
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armv7_init_nonsec();
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#ifdef CONFIG_U_QE
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u_qe_resume();
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#endif
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#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
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ls1_psci_resume_fixup();
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#endif
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}
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int fsl_dp_resume(void)
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{
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u32 start_addr;
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void (*kernel_resume)(void);
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
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if (!is_warm_boot())
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return 0;
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dp_resume_prepare();
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/* Get the entry address and jump to kernel */
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start_addr = in_le32(&scfg->sparecr[3]);
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debug("Entry address is 0x%08x\n", start_addr);
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kernel_resume = (void (*)(void))start_addr;
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secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
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return 0;
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}
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