mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-10-31 00:11:51 +01:00
660d5f0d49
"reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU. This change is a preparation to submission of ARCv2 architecture port. Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones). So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
48 lines
872 B
C
48 lines
872 B
C
/*
|
|
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/arcregs.h>
|
|
#include <asm/cache.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int arch_cpu_init(void)
|
|
{
|
|
#ifdef CONFIG_SYS_ICACHE_OFF
|
|
icache_disable();
|
|
#else
|
|
icache_enable();
|
|
invalidate_icache_all();
|
|
#endif
|
|
|
|
flush_dcache_all();
|
|
#ifdef CONFIG_SYS_DCACHE_OFF
|
|
dcache_disable();
|
|
#else
|
|
dcache_enable();
|
|
#endif
|
|
timer_init();
|
|
|
|
/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
|
|
if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
|
|
gd->arch.running_on_hw = 0;
|
|
else
|
|
gd->arch.running_on_hw = 1;
|
|
|
|
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
|
|
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int arch_early_init_r(void)
|
|
{
|
|
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
|
|
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
|
|
return 0;
|
|
}
|