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	Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to.  This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value.  Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g.  COLD vs WARM resets).  As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely.  Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
    @@
    expression argvalue;
    @@
    - reset_cpu(argvalue)
    + reset_cpu()
    @@
    identifier argname;
    type argtype;
    @@
    - reset_cpu(argtype argname)
    + reset_cpu(void)
    { ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
		
	
			
		
			
				
	
	
		
			36 lines
		
	
	
		
			767 B
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			36 lines
		
	
	
		
			767 B
		
	
	
	
		
			C
		
	
	
	
	
	
// SPDX-License-Identifier: GPL-2.0+
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/*
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 * Copyright (C) 2012-2014 Panasonic Corporation
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 * Copyright (C) 2015-2016 Socionext Inc.
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 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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 */
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#include <cpu_func.h>
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#include <linux/io.h>
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#include <asm/secure.h>
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#include "sc-regs.h"
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/* If PSCI is enabled, this is used for SYSTEM_RESET function */
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#ifdef CONFIG_ARMV7_PSCI
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#define __SECURE	__secure
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#else
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#define __SECURE
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#endif
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void __SECURE reset_cpu(void)
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{
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	u32 tmp;
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	writel(5, sc_base + SC_IRQTIMSET); /* default value */
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	tmp  = readl(sc_base + SC_SLFRSTSEL);
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	tmp &= ~0x3; /* mask [1:0] */
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	tmp |= 0x0;  /* XRST reboot */
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	writel(tmp, sc_base + SC_SLFRSTSEL);
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	tmp = readl(sc_base + SC_SLFRSTCTL);
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	tmp |= 0x1;
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	writel(tmp, sc_base + SC_SLFRSTCTL);
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}
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