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b3af1d698b
Due to recent changes to the NET support on U-boot, DM9000 is no longer detected on the DM355 EVM. This minor update enables DM9000 on the DM355 EVM. Tested on the DM355 EVM Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
117 lines
3.2 KiB
C
117 lines
3.2 KiB
C
/*
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* Copyright (C) 2009 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emif_defs.h>
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#include <asm/arch/nand_defs.h>
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#include "../common/misc.h"
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#include <net.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* With the DM355 EVM, u-boot is *always* a third stage loader,
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* unless a JTAG debugger handles the first two stages:
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*
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* - 1st stage is ROM Boot Loader (RBL), which searches for a
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* second stage loader in one of three places based on SW7:
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* NAND (with MMC/SD fallback), MMC/SD, or UART.
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*
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* - 2nd stage is User Boot Loader (UBL), using at most 30KB
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* of on-chip SRAM, responsible for lowlevel init, and for
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* loading the third stage loader into DRAM.
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*
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* - 3rd stage, that's us!
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*/
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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/* We expect the UBL to have handled "lowlevel init", which
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* involves setting up at least:
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* - clocks
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* + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
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* + clock divisors for those PLLs
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* + LPSC_DDR module enabled
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* + LPSC_TIMER0 module (still) enabled
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* - EMIF
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* + DDR init and timings
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* + AEMIF timings (for NAND and DM9000)
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* - pinmux
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*
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* Some of that is repeated here, mostly as a precaution.
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*/
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/* AEMIF: Some "address" lines are available as GPIOs. A3..A13
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* could be too if we used A12 as a GPIO during NAND chipselect
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* (and Linux did too), letting us control the LED on A7/GPIO61.
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*/
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REG(PINMUX2) = 0x0c08;
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/* UART0 may still be in SyncReset if we didn't boot from UART */
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davinci_enable_uart0();
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/* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
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lpsc_on(DAVINCI_LPSC_TPCC);
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lpsc_on(DAVINCI_LPSC_TPTC0);
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lpsc_on(DAVINCI_LPSC_TPTC1);
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return 0;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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#ifdef CONFIG_NAND_DAVINCI
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static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
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{
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struct nand_chip *this = mtd->priv;
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u32 wbase = (u32) this->IO_ADDR_W;
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u32 rbase = (u32) this->IO_ADDR_R;
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if (chip == 1) {
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__set_bit(14, &wbase);
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__set_bit(14, &rbase);
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} else {
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__clear_bit(14, &wbase);
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__clear_bit(14, &rbase);
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}
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this->IO_ADDR_W = (void *)wbase;
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this->IO_ADDR_R = (void *)rbase;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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davinci_nand_init(nand);
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nand->select_chip = nand_dm355evm_select_chip;
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return 0;
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}
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#endif
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