mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-10-25 06:21:47 +02:00
43e568c4ae
During boot, U-Boot raises the CPU frequency but the CORE and MPU regulators are not updated. This is not a problem in cold boot since the default values that the pmic outputs are correct, but if Linux were to switch the module to a low power OPP, the new voltage values will be retained after a reboot and the module will likely hang once U-Boot raises the CPU frequency back up. Set both CORE and MPU regulators to to 1.1V on boot. Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
138 lines
3.3 KiB
C
138 lines
3.3 KiB
C
/*
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* Copyright (C) 2016 Compulab, Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <i2c.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/gpio.h>
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#include <power/pmic.h>
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#include <power/tps65218.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
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const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
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const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
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const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
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const struct ctrl_ioregs ioregs_ddr3 = {
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.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
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.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
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.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
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.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.emif_sdram_config_ext = 0x0143,
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};
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/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
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struct emif_regs ddr3_emif_regs = {
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.sdram_config = 0x638413B2,
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.ref_ctrl = 0x00000C30,
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.sdram_tim1 = 0xEAAAD4DB,
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.sdram_tim2 = 0x266B7FDA,
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.sdram_tim3 = 0x107F8678,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x50074BE4,
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.temp_alert_config = 0x0,
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.emif_ddr_phy_ctlr_1 = 0x0E004008,
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.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x00000066,
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.emif_ddr_ext_phy_ctrl_3 = 0x00000091,
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.emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
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.emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
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.emif_rd_wr_exec_thresh = 0x80000405,
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.emif_prio_class_serv_map = 0x80000001,
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.emif_connect_id_serv_1_map = 0x80000094,
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.emif_connect_id_serv_2_map = 0x00000000,
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.emif_cos_config = 0x000FFFFF
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};
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const u32 ext_phy_ctrl_const_base_ddr3[] = {
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0x00000000,
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0x00000044,
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0x00000044,
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0x00000046,
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0x00000046,
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0x00000000,
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0x00000059,
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0x00000077,
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0x00000093,
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0x000000A8,
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0x00000000,
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0x00000019,
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0x00000037,
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0x00000053,
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0x00000068,
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0x00000000,
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0x0,
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0x0,
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0x40000000,
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0x08102040
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};
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void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
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{
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*regs = ext_phy_ctrl_const_base_ddr3;
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*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr;
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}
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const struct dpll_params *get_dpll_mpu_params(void)
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{
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return &dpll_mpu;
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}
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const struct dpll_params *get_dpll_core_params(void)
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{
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return &dpll_core;
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}
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const struct dpll_params *get_dpll_per_params(void)
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{
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return &dpll_per;
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}
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void scale_vcores(void)
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{
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set_i2c_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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if (i2c_probe(TPS65218_CHIP_PM))
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return;
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tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV);
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tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV);
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}
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void sdram_init(void)
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{
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unsigned long ram_size;
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config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
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ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (ram_size == 0x80000000 ||
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ram_size == 0x40000000 ||
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ram_size == 0x20000000)
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return;
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ddr3_emif_regs.sdram_config = 0x638453B2;
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config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
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ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (ram_size == 0x08000000)
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return;
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hang();
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}
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