Shengzhou Liu 019a147b65 driver/ddr/fsl: Add workaround for erratum A-010165 ...

During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

2016-05-18 08:51:47 -07:00

..

clock.h

armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-29 10:34:00 -07:00

config.h

driver/ddr/fsl: Add workaround for erratum A-010165

2016-05-18 08:51:47 -07:00

cpu.h

armv8: LS2080A: Consolidate LS2080A and LS2085A

2016-04-06 10:26:46 -07:00

fdt.h

armv8/ls1043aqds: add LS1043AQDS board support

2015-11-30 09:11:10 -08:00

fsl_serdes.h

armv8: LS2080A: Consolidate LS2080A and LS2085A

2016-04-06 10:26:46 -07:00

immap_lsch2.h

arch/arm: add SEC JR0 offset

2016-05-18 08:51:46 -07:00

immap_lsch3.h

arch/arm: add SEC JR0 offset

2016-05-18 08:51:46 -07:00

imx-regs.h

armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-29 10:34:00 -07:00

ls2080a_stream_id.h

armv8: ls2080a: update stream ID partitioning info

2016-03-21 12:42:12 -07:00

mmu.h

armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-29 10:34:00 -07:00

mp.h

armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-29 10:34:00 -07:00

ns_access.h

armv8/fsl_lsch2: Add fsl_lsch2 SoC

2015-10-29 10:34:00 -07:00

soc.h

armv8: LS2080A: Consolidate LS2080A and LS2085A

2016-04-06 10:26:46 -07:00

speed.h

armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-29 10:34:00 -07:00