mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-12-19 00:11:30 +01:00
4146a31dce
Currently xilinx_pm_request API supports four u32 payloads. However the legacy SMC format supports five u32 request payloads and extended SMC format supports six u32 request payloads. Add support for the same in xilinx_pm_request API. Also add two dummy arguments to all the callers of xilinx_pm_request. The TF-A always fills seven u32 return payload so add support for the same in xilinx_pm_request API. Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
60 lines
1.3 KiB
C
60 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* (C) Copyright 2019, Xilinx, Inc,
|
|
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
|
|
*/
|
|
|
|
#include <cpu_func.h>
|
|
#include <log.h>
|
|
#include <memalign.h>
|
|
#include <versalpl.h>
|
|
#include <zynqmp_firmware.h>
|
|
#include <asm/cache.h>
|
|
|
|
static ulong versal_align_dma_buffer(ulong *buf, u32 len)
|
|
{
|
|
ulong *new_buf;
|
|
|
|
if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
|
|
new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
|
|
memcpy(new_buf, buf, len);
|
|
buf = new_buf;
|
|
}
|
|
|
|
return (ulong)buf;
|
|
}
|
|
|
|
static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
|
bitstream_type bstype, int flags)
|
|
{
|
|
ulong bin_buf;
|
|
int ret;
|
|
u32 buf_lo, buf_hi;
|
|
u32 ret_payload[PAYLOAD_ARG_CNT];
|
|
|
|
bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
|
|
|
|
debug("%s called!\n", __func__);
|
|
flush_dcache_range(bin_buf, bin_buf + bsize);
|
|
|
|
buf_lo = lower_32_bits(bin_buf);
|
|
buf_hi = upper_32_bits(bin_buf);
|
|
|
|
if (desc->family == xilinx_versal2) {
|
|
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi,
|
|
buf_lo, 0, 0, 0, ret_payload);
|
|
} else {
|
|
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
|
|
buf_hi, 0, 0, 0, ret_payload);
|
|
}
|
|
|
|
if (ret)
|
|
printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
struct xilinx_fpga_op versal_op = {
|
|
.load = versal_load,
|
|
};
|