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7872a986e5
Since we use SPEED GRADE fuse to set A55 frequency, remove the set_arm_core_low_drive_clk function which has hard coded frequency. And adjust clock_init called sequence and split it to early and late functions. Set the authen register in early function, because CCF driver checks NS bit. Set bus and core clock in late function, because the fuse read and SoC type/rev depend on ELE. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
156 lines
3.1 KiB
C
156 lines
3.1 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 PHYTEC Messtechnik GmbH
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* Author: Christoph Stoidner <c.stoidner@phytec.de>
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* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/mu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/trdc.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/ele_api.h>
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#include <asm/sections.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Will be part of drivers/power/regulator/pca9450.c
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* when pca9451a support is added.
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*/
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#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_board_init(void)
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{
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int ret;
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ret = ele_start_rng();
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if (ret)
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printf("Fail to start RNG: %d\n", ret);
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puts("Normal Boot\n");
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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unsigned int val = 0;
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ret = pmic_get("pmic@25", &dev);
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if (ret == -ENODEV) {
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puts("No pca9450@25\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/* enable DVS control through PMIC_STBY_REQ */
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
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if (ret < 0)
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return ret;
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val = ret;
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if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) {
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/* 0.8v for Low drive mode */
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if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
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pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
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} else {
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
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pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x10);
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}
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} else {
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/* 0.9v for Over drive mode */
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if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
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pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x14);
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} else {
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
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pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
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}
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}
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/* set standby voltage to 0.65v */
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if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
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else
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
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/* I2C_LT_EN*/
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pmic_reg_write(dev, 0xa, 0x3);
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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timer_init();
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arch_cpu_init();
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spl_early_init();
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preloader_console_init();
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ret = imx9_probe_mu();
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if (ret) {
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printf("Fail to init ELE API\n");
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} else {
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debug("SOC: 0x%x\n", gd->arch.soc_rev);
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debug("LC: 0x%x\n", gd->arch.lifecycle);
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}
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clock_init_late();
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power_init_board();
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if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
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set_arm_core_max_clk();
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/* Init power of mix */
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soc_power_init();
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/* Setup TRDC for DDR access */
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trdc_init();
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/* DDR initialization */
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spl_dram_init();
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/* Put M33 into CPUWAIT for following kick */
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ret = m33_prepare();
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if (!ret)
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printf("M33 prepare ok\n");
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board_init_r(NULL, 0);
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}
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