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https://source.denx.de/u-boot/u-boot.git
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97833f4cf6
Move unnecessary clock frequency assignment out of device-tree and into the board config header so that the ns16550 serial driver can successfully init during SPL after failing to resolve the parent clock from upstream dts. The serial driver will then resolve clock frequency from device-tree node parent clock at init during Main app as it is expected by upstream. Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*
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*/
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#ifndef _STARFIVE_VISIONFIVE2_H
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#define _STARFIVE_VISIONFIVE2_H
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#define RISCV_MMODE_TIMERBASE 0x2000000
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#define RISCV_MMODE_TIMEROFF 0xbff8
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#define RISCV_MMODE_TIMER_FREQ 4000000
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#define RISCV_SMODE_TIMER_FREQ 4000000
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#define __io
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#define TYPE_GUID_SPL "2E54B353-1271-4842-806F-E436D6AF6985"
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#define TYPE_GUID_UBOOT "BC13C2FF-59E6-4262-A352-B275FD6F7172"
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#define TYPE_GUID_SYSTEM "EBD0A0A2-B9E5-4433-87C0-68B6B72699C7"
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#define PARTS_DEFAULT \
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"name=spl,start=2M,size=2M,type=${type_guid_gpt_loader1};" \
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"name=uboot,size=4MB,type=${type_guid_gpt_loader2};" \
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"name=system,size=-,bootable,type=${type_guid_gpt_system};"
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#define CFG_EXTRA_ENV_SETTINGS \
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"kernel_addr_r=0x40200000\0" \
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"kernel_comp_addr_r=0x88000000\0" \
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"kernel_comp_size=0x4000000\0" \
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"fdt_addr_r=0x46000000\0" \
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"fdtoverlay_addr_r=0x45800000\0" \
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"scriptaddr=0x43900000\0" \
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"pxefile_addr_r=0x45900000\0" \
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"ramdisk_addr_r=0x46100000\0" \
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"type_guid_gpt_loader1=" TYPE_GUID_SPL "\0" \
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"type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \
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"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
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"partitions=" PARTS_DEFAULT "\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
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#define CFG_SYS_NS16550_CLK 24000000
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#endif /* _STARFIVE_VISIONFIVE2_H */
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