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- Add SPI flashes support - Add RIFSC system bus driver fixes -----BEGIN PGP SIGNATURE----- iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmjM+FUcHHBhdHJpY2Uu Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pv1vD/4zc1b2iCTZf2LIppeq dpDM2eHbqcyM02vQ12uxk2R6ZMUPZoSb4Rd4Icra6HpCxCR/wnoQ6dxIQzpUWBv+ fheVXP6BVz71jC2RrfR2CysSArvABE4bSAkJvdq7SJXB/ED+F0cV+8PsvXdunRlD PEEkKK6kC2N+mOsH/iIwE79e8XY8/UD4fEqUJQ8ifjllNXCsPjvLWFvZEt9ihCQ9 2W9KVWytIH/pTyiYyQMJa1ImUUOqgI2a6Lz/I2lxRPE9GNJor/A30Eh4Y8iYr7gi kRWUXDburQe3KHF4+XqRfzrR4VeQIEz000Kiu7nIxRduwlKTcTUWqrRbWcSfPRwi UyurMYs+7RJ4KnPQt21H/jLbF5+6QvlBnvYBEFFLNN0KIrvzBUVIXyvomz7TavQP vC+z/mdO3OeXeNiEPWv2KWvQ+h2OBtIHf+zLFqS08DD5nTtsnjnUmNg05BNHY987 i/xXLIJdvFkaviaThV396mQgTAVi4ICw29bB8akOLtI8ssq4ODHdltS1RhhSUdYG PkEVzK08Q4ZvKeUAbBh/mVCPmK5eCT+idkbasO0NQjs9IdMfQnTazex8suS1BITs D28Af/zWGr5bYxIVY+HGA67CqT6RCTuz92JZ1WYWaPE94eHP/zD1DzABbk0AdJ56 Olgcy7wsk7F4L7F3eZHYQiQ/YA== =1zWq -----END PGP SIGNATURE----- Merge tag 'u-boot-stm32-20250919' of https://source.denx.de/u-boot/custodians/u-boot-stm into next CI: - https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27668 STM32MP2: - Add SPI flashes support - Add RIFSC system bus driver fixes
87 lines
3.1 KiB
Plaintext
87 lines
3.1 KiB
Plaintext
#
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# Memory devices
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#
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menu "Memory Controller drivers"
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config MEMORY
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bool "Enable Driver Model for Memory Controller drivers"
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depends on DM
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help
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Enable driver model for Memory Controller devices.
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These devices provide Memory bus interface to various devices like
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SRAM, Ethernet adapters, FPGAs, etc.
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For now this uclass has no methods yet.
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config ATMEL_EBI
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bool "Support for Atmel EBI"
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help
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Driver for Atmel EBI controller. This is a dummy
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driver. Doesn't provide an access to EBI controller. Select
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this option to enable the NAND flash controller driver
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config SANDBOX_MEMORY
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bool "Enable Sandbox Memory Controller driver"
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depends on SANDBOX && MEMORY
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help
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This is a driver model based Memory Controller driver for sandbox.
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Currently it is a stub only, as there are no usable uclass methods
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yet.
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config STM32_FMC2_EBI
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bool "Support for FMC2 External Bus Interface on STM32MP SoCs"
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depends on ARCH_STM32MP
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help
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Select this option to enable the STM32 FMC2 External Bus Interface
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controller. This driver configures the transactions with external
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devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
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SOCs containing the FMC2 External Bus Interface.
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config STM32_OMM
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bool "STM32 Octo Memory Manager"
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depends on ARCH_STM32MP
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help
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This driver manages the muxing between the 2 OSPI busses and
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the 2 output ports. There are 4 possible muxing configurations:
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- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
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output is on port 2
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- OSPI1 and OSPI2 are multiplexed over the same output port 1
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- swapped mode (no multiplexing), OSPI1 output is on port 2,
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OSPI2 output is on port 1
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- OSPI1 and OSPI2 are multiplexed over the same output port 2
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It also manages :
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- the split of the memory area shared between the 2 OSPI instances.
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- chip select selection override.
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- the time between 2 transactions in multiplexed mode.
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config TI_AEMIF
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tristate "Texas Instruments AEMIF driver"
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depends on ARCH_KEYSTONE || ARCH_DAVINCI
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help
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This driver is for the AEMIF module available in Texas Instruments
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SoCs. AEMIF stands for Asynchronous External Memory Interface and
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is intended to provide a glue-less interface to a variety of
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asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
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of 256M bytes of any of these memories can be accessed at a given
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time via four chip selects with 64M byte access per chip select.
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config TI_GPMC
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bool "Texas Instruments GPMC driver"
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depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
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depends on MEMORY && CLK && OF_CONTROL
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help
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This driver is for the General Purpose Memory Controller (GPMC)
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present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
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interfacing to a variety of asynchronous as well as synchronous
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memory drives like NOR, NAND, OneNAND, SRAM.
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if TI_GPMC
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config TI_GPMC_DEBUG
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bool "Debug Texas Instruments GPMC timings"
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help
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Enable this to print GPMC timings before and after the GPMC registers
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are programmed. This should not be left enabled on production systems.
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endif
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endmenu
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