Dinesh Maniyam 1ae1e9c55e dt: nand: add cadence nand dt-bindings ...

The Cadence NAND is a configurable mtd raw block which
supports multiple options for chipsets, clocking and reset structure, and
feature list.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>

2025-03-15 10:35:00 +01:00

..

spi

sf: Rename sf_params.c to spi_flash_ids.c

2016-11-18 13:04:54 +05:30

altera_qspi.txt

mtd: add altera quadspi driver

2015-11-12 08:26:58 +08:00

cadence,nand.yaml

dt: nand: add cadence nand dt-bindings

2025-03-15 10:35:00 +01:00

mtd-physmap.txt

…

spi-nand.txt

dt-bindings: Add bindings for SPI NAND devices

2018-09-20 20:10:49 +05:30

ti,elm.yaml

dt-bindings: mtd: Add ti, elm DT binding documentation

2023-01-08 10:38:50 +01:00

ti,gpmc-nand.yaml

dt-bindings: mtd: Add ti, gpmc-nand DT binding documentation

2023-01-08 10:38:50 +01:00