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d116b53f87
The Intel SIPI (start-up inter-processor interrupt) vector is the entry point for each secondary CPU (also called an AP - applications processor). The assembler and C code are linked, so add comments to indicate this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
218 lines
4.4 KiB
ArmAsm
218 lines
4.4 KiB
ArmAsm
/*
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* Copyright (c) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* Taken from coreboot file of the same name
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*/
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/*
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* The SIPI vector is responsible for initializing the APs in the sytem. It
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* loads microcode, sets up MSRs, and enables caching before calling into
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* C code
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*/
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#include <asm/global_data.h>
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#include <asm/msr-index.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/sipi.h>
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#define CODE_SEG (X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE)
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#define DATA_SEG (X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE)
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/*
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* First we have the 16-bit section. Every AP process starts here.
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* The simple task is to load U-Boot's Global Descriptor Table (GDT) to allow
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* U-Boot's 32-bit code to become visible, then jump to ap_start.
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*
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* Note that this code is copied to RAM below 1MB in mp_init.c, and runs from
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* there, but the 32-bit code (ap_start and onwards) is part of U-Boot and
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* is therefore relocated to the top of RAM with other U-Boot code. This
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* means that for the 16-bit code we must write relocatable code, but for the
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* rest, we can do what we like.
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*/
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.text
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.code16
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.globl ap_start16
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ap_start16:
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cli
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB */
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/* setup the data segment */
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movw %cs, %ax
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movw %ax, %ds
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/* Use an address relative to the data segment for the GDT */
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movl $gdtaddr, %ebx
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subl $ap_start16, %ebx
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data32 lgdt (%ebx)
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movl %cr0, %eax
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andl $(~(X86_CR0_PG | X86_CR0_AM | X86_CR0_WP | X86_CR0_NE | \
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X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)), %eax
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orl $(X86_CR0_NW | X86_CR0_CD | X86_CR0_PE), %eax
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movl %eax, %cr0
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movl $ap_start_jmp, %eax
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subl $ap_start16, %eax
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movw %ax, %bp
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/* Jump to ap_start within U-Boot */
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data32 cs ljmp *(%bp)
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.align 4
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.globl sipi_params_16bit
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sipi_params_16bit:
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/* 48-bit far pointer */
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ap_start_jmp:
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.long 0 /* offset set to ap_start by U-Boot */
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.word CODE_SEG /* segment */
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.word 0 /* padding */
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gdtaddr:
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.word 0 /* limit */
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.long 0 /* table */
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.word 0 /* unused */
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.globl ap_start16_code_end
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ap_start16_code_end:
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/*
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* Set up the special 'fs' segment for global_data. Then jump to ap_continue
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* to set up the AP.
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*/
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.globl ap_start
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ap_start:
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.code32
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movw $DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %gs
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movw $(X86_GDT_ENTRY_32BIT_FS * X86_GDT_ENTRY_SIZE), %ax
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movw %ax, %fs
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/* Load the Interrupt descriptor table */
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mov idt_ptr, %ebx
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lidt (%ebx)
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/* Obtain cpu number */
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movl ap_count, %eax
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1:
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movl %eax, %ecx
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inc %ecx
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lock cmpxchg %ecx, ap_count
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jnz 1b
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/* Setup stacks for each CPU */
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movl stack_size, %eax
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mul %ecx
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movl stack_top, %edx
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subl %eax, %edx
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mov %edx, %esp
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/* Save cpu number */
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mov %ecx, %esi
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/* Determine if one should check microcode versions */
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mov microcode_ptr, %edi
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test %edi, %edi
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jz microcode_done /* Bypass if no microde exists */
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/* Get the Microcode version */
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mov $1, %eax
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cpuid
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mov $MSR_IA32_UCODE_REV, %ecx
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rdmsr
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/* If something already loaded skip loading again */
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test %edx, %edx
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jnz microcode_done
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/* Determine if parallel microcode loading is allowed */
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cmp $0xffffffff, microcode_lock
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je load_microcode
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/* Protect microcode loading */
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lock_microcode:
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lock bts $0, microcode_lock
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jc lock_microcode
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load_microcode:
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/* Load new microcode */
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mov $MSR_IA32_UCODE_WRITE, %ecx
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xor %edx, %edx
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mov %edi, %eax
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/*
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* The microcode pointer is passed in pointing to the header. Adjust
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* pointer to reflect the payload (header size is 48 bytes)
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*/
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add $UCODE_HEADER_LEN, %eax
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pusha
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wrmsr
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popa
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/* Unconditionally unlock microcode loading */
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cmp $0xffffffff, microcode_lock
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je microcode_done
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xor %eax, %eax
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mov %eax, microcode_lock
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microcode_done:
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/*
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* Load MSRs. Each entry in the table consists of:
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* 0: index,
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* 4: value[31:0]
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* 8: value[63:32]
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* See struct saved_msr in mp_init.c.
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*/
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mov msr_table_ptr, %edi
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mov msr_count, %ebx
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test %ebx, %ebx
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jz 1f
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load_msr:
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mov (%edi), %ecx
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mov 4(%edi), %eax
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mov 8(%edi), %edx
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wrmsr
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add $12, %edi
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dec %ebx
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jnz load_msr
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1:
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/* Enable caching */
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mov %cr0, %eax
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andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
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mov %eax, %cr0
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/* c_handler(cpu_num) */
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movl %esi, %eax /* cpu_num */
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mov c_handler, %esi
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call *%esi
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/* This matches struct sipi_param */
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.align 4
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.globl sipi_params
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sipi_params:
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idt_ptr:
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.long 0
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stack_top:
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.long 0
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stack_size:
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.long 0
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microcode_lock:
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.long 0
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microcode_ptr:
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.long 0
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msr_table_ptr:
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.long 0
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msr_count:
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.long 0
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c_handler:
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.long 0
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ap_count:
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.long 0
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