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	Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
		
			
				
	
	
		
			46 lines
		
	
	
		
			946 B
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			46 lines
		
	
	
		
			946 B
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
| /*
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|  * MIPS Coherence Manager (CM) Initialisation
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|  *
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|  * Copyright (c) 2016 Imagination Technologies Ltd.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <asm/addrspace.h>
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| #include <asm/asm.h>
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| #include <asm/cm.h>
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| #include <asm/mipsregs.h>
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| #include <asm/regdef.h>
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| 
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| LEAF(mips_cm_map)
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| 	/* Config3 must exist for a CM to be present */
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| 	mfc0		t0, CP0_CONFIG, 1
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| 	bgez		t0, 2f
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| 	mfc0		t0, CP0_CONFIG, 2
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| 	bgez		t0, 2f
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| 
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| 	/* Check Config3.CMGCR to determine CM presence */
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| 	mfc0		t0, CP0_CONFIG, 3
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| 	and		t0, t0, MIPS_CONF3_CMGCR
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| 	beqz		t0, 2f
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| 
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| 	/* Find the current physical GCR base address */
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| 1:	MFC0		t0, CP0_CMGCRBASE
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| 	PTR_SLL		t0, t0, 4
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| 
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| 	/* If the GCRs are where we want, we're done */
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| 	PTR_LI		t1, CONFIG_MIPS_CM_BASE
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| 	beq		t0, t1, 2f
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| 
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| 	/* Move the GCRs to our configured base address */
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| 	PTR_LI		t2, CKSEG1
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| 	PTR_ADDU	t0, t0, t2
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| 	sw		zero, GCR_BASE_UPPER(t0)
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| 	sw		t1, GCR_BASE(t0)
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| 
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| 	/* Re-check the GCR base */
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| 	b		1b
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| 
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| 2:	jr		ra
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| 	END(mips_cm_map)
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