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983e37007d
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
/*
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* (C) Copyright 2011
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Tom Rini <trini@ti.com>
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*
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* Initial Code from:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Jian Zhang <jzhang@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <jffs2/load_kernel.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/omap_gpmc.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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/*
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* Many boards will want to know the results of the NAND_CMD_READID command
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* in order to decide what to do about DDR initialization. This function
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* allows us to do that very early and to pass those results back to the
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* board so it can make whatever decisions need to be made.
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*/
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int identify_nand_chip(int *mfr, int *id)
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{
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int loops = 1000;
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/* Make sure that we have setup GPMC for NAND correctly. */
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set_gpmc_cs0(MTD_DEV_TYPE_NAND);
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sdelay(2000);
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/* Issue a RESET and then READID */
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writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
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writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
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while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
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!= NAND_STATUS_READY) {
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sdelay(100);
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if (--loops == 0)
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return 1;
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}
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writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
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/* Set the address to read to 0x0 */
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writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
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/* Read off the manufacturer and device id. */
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*mfr = readb(&gpmc_cfg->cs[0].nand_dat);
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*id = readb(&gpmc_cfg->cs[0].nand_dat);
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return 0;
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}
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