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8f975865be
This solves issues when larger amount of DRAM is used, like 256MB. Behave the same in case of CPU bypass as we do in case of EMI bypass, but wait 15 ms. We need to wait until the clock domain stabilizes. This issue seemed to have been caused by not waiting after frobbing with the CPU bypass, it was unrelated to memory, but had a direct impact, causing trouble. This was yet another X-File of the imx-bootlets, sigh. The conclusion is, trying a semi-random delay (there is delay after the EMI bypass change), the issue is fixed. Another possible explanation is that we do not do the "simple memory test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of the memory, while also outputing something on the serial port). This might have caused the similar delay in the imx-bootlets and therefore they didn't need to add this explicitly. For now, this seems good fix enough, but to me, whole that memory init code in imx-bootlets is completely flunked and it'd need deeper investigation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
247 lines
7.3 KiB
C
247 lines
7.3 KiB
C
/*
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* Freescale i.MX28 RAM init
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include "mx28_init.h"
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uint32_t dram_vals[] = {
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000100, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00010101, 0x01010101,
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0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
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0x00000100, 0x00000100, 0x00000000, 0x00000002,
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0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
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0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
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0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
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0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
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0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
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0x00000003, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000612, 0x01000F02,
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0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
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0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
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0x07000300, 0x07000300, 0x07000300, 0x00000006,
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0x00000000, 0x00000000, 0x01000000, 0x01020408,
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0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
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0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
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0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00010000, 0x00020304,
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0x00000004, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x01010000,
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0x01000000, 0x03030000, 0x00010303, 0x01020202,
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0x00000000, 0x02040303, 0x21002103, 0x00061200,
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0x06120612, 0x04320432, 0x04320432, 0x00040004,
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0x00040004, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00010001
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};
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void init_m28_200mhz_ddr2(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
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writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
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}
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void mx28_mem_init_clock(void)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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/* Gate EMI clock */
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
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/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
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writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
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&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
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/* Ungate EMI clock */
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
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early_delay(11000);
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/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
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writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
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(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
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&clkctrl_regs->hw_clkctrl_emi);
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/* Unbypass EMI */
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writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
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&clkctrl_regs->hw_clkctrl_clkseq_clr);
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early_delay(10000);
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}
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void mx28_mem_setup_cpu_and_hbus(void)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
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* and ungate CPU clock */
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writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
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(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
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/* Set CPU bypass */
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writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
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&clkctrl_regs->hw_clkctrl_clkseq_set);
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/* HBUS = 151MHz */
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writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
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writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
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&clkctrl_regs->hw_clkctrl_hbus_clr);
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early_delay(10000);
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/* CPU clock divider = 1 */
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
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CLKCTRL_CPU_DIV_CPU_MASK, 1);
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/* Disable CPU bypass */
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writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
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&clkctrl_regs->hw_clkctrl_clkseq_clr);
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early_delay(15000);
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}
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void mx28_mem_setup_vdda(void)
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{
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struct mx28_power_regs *power_regs =
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(struct mx28_power_regs *)MXS_POWER_BASE;
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writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
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(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
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POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
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&power_regs->hw_power_vddactrl);
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}
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void mx28_mem_setup_vddd(void)
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{
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struct mx28_power_regs *power_regs =
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(struct mx28_power_regs *)MXS_POWER_BASE;
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writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
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(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
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POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
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&power_regs->hw_power_vdddctrl);
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}
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void mx28_mem_get_size(void)
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{
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struct mx28_digctl_regs *digctl_regs =
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(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
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uint32_t sz, da;
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uint32_t *vt = (uint32_t *)0x20;
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/* The following is "subs pc, r14, #4", used as return from DABT. */
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const uint32_t data_abort_memdetect_handler = 0xe25ef004;
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/* Replace the DABT handler. */
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da = vt[4];
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vt[4] = data_abort_memdetect_handler;
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sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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writel(sz, &digctl_regs->hw_digctl_scratch0);
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writel(sz, &digctl_regs->hw_digctl_scratch1);
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/* Restore the old DABT handler. */
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vt[4] = da;
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}
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void mx28_mem_init(void)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct mx28_pinctrl_regs *pinctrl_regs =
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(struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
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/* Set DDR2 mode */
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writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
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&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
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/* Power up PLL0 */
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writel(CLKCTRL_PLL0CTRL0_POWER,
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&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
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early_delay(11000);
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mx28_mem_init_clock();
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mx28_mem_setup_vdda();
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/*
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* Configure the DRAM registers
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*/
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/* Clear START bit from DRAM_CTL16 */
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clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
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init_m28_200mhz_ddr2();
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/* Clear SREFRESH bit from DRAM_CTL17 */
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clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
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/* Set START bit in DRAM_CTL16 */
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setbits_le32(MXS_DRAM_BASE + 0x40, 1);
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/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
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while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
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;
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mx28_mem_setup_vddd();
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early_delay(10000);
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mx28_mem_setup_cpu_and_hbus();
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mx28_mem_get_size();
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}
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